User`s manual

RTD Embedded Technologies, Inc. | www.rtd.com 25 FPGA35S6 User’s Manual
6 Register Address Space
This is the register address space for the example FPGA that is given with the FPGA35S6.
6.1 BAR0 – FPGA Example Register Map
Table 16: FPGA Example Register Map
Offset
0x03
0x02
0x01
0x00
0x00
R_ID
0x04
R_STATUS
0x08
R_EEPROM
0x10
R_PORT0_IN
0x14
R_PORT0_OUT
0x18
R_PORT0_DIR
0x20
R_PORT1_IN
0x24
R_PORT1_OUT
0x28
R_PORT1_DIR
0x30
R_PORT2L_IN
0x34
R_PORT2L_OUT
0x38
R_PORT2L_DIR
0x40
R_PORT2H_IN
0x44
R_PORT2H_OUT
0x48
R_PORT2H_DIR
0x50
R_DDR_RD_DATA
0x54
R_DDR_WR_DATA
0x58
R_DDR_ADDR
0x5C
R_DDR_STATUS
0x60
R_CLK_27_1
0x64
R_CLK_27_2
6.1.1 R_ID (READ)
This is a register that identifies the board.
0x12345678 is the identification of the example code
6.1.2 R_STATUS (READ)
This is a status register for power good (pgood) for the power supplies and serial out from the EEPROM
B0: EEPROM Serial out
B4: 1.2V pgood
B5: 1.8V pgood
B6: 3.3V pgood
6.1.3 R_EEPROM (READ/WRITE)
This register has the outputs to the EEPROM.
B0: EEPROM Serial Clock
B1: EEPROM Serial Input
B2: EEPROM Chip Select