User`s manual

RTD Embedded Technologies, Inc. | www.rtd.com 7 FPGA35S6 User’s Manual
1 Introduction
1.1 Product Overview
The FPGA35S6 series of FPGA boards are designed to provide platform to create any digital I/O that is required for
your application. It interfaces with the PCIe bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and
1Gb of DDR2 SDRAM. There 48 5V tolerant I/O and 40 3.3V tolerant high speed I/O.
1.2 Board Features
 Xilinx Spartan 6 System level features
o XC6SLX45T
 43,661 Logic Cells
 2,489 kb of internal RAM
 116 18Kb (2088 Kb Max) Block RAM
 401 kB Distributed RAM
o XC6SLX100T
 101,261 Logic Cells
 5,800 kb of internal RAM
 268 18Kb (4,824 Kb Max) Block RAM
 976 kB Distributed RAM
o RAM hierarchical memory:
 Each block RAM has two independent ports
 Programmable Data Width
o Integrated Endpoint block for PCI Express
o Integrated Memory Controller
 1 Gb of DDR2 SDRAM
 Supports access rates of up to 800Mb/s
o Dedicated carry logic for high-speed arithmetic
o Abundant logic resources with increased logic capacity
 Optional shift register or distributed RAM support
 Efficient 6-input LUTs
 LUT with dual flip-flops
o Four dedicated DLLs for advanced clock control
 Phase shift input clock by 0, 90, 180, 270
 Multiply input clock by 2 to 32
 Divide input clock by 1 to 32
 Fully supported by Xilinx development system
o ISE WebPACK (free download from http://www.xilinx.com)
o ISE Design Suite
 Digital I/O Connectors
o 48 5 volt tolerant I/O with ESD protection
o 40 3.3 volt tolerant high speed I/O with ESD protection
 PCI Express Bus:
o PCIe/104 Universal Board
 Interfaces with Type 1 or Type 2 bus
 No re-population
o Provides 2.5 Gbps in each direction
o In-band interrupts and messages
o Message Signaled Interrupt (MSI) support