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1. General description

The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)

with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily

cascaded for larger LCD applications. The PCF8534A is compatible with most

microcontrollers and communicates via the two-line bidirectional I

C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

• PCF8534AHL/1 should not be used for new design-ins. Replacement part is

PCF85134HL/1

2. Features and benefits

 AEC-Q100 compliant (PCF8534AH/1) for automotive applications

 Single-chip LCD controller and driver

 Selectable backplane drive configurations: static or 2, 3, or 4 backplane multiplexing

 60 segment outputs allowing to drive:

 30 7-segment numeric characters

 15 14-segment alphanumeric characters

 Any graphics of up to 240 elements

 Cascading supported for larger applications

 60  4-bit display data storage RAM

 Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high

threshold twisted nematic LCDs

 Internal LCD bias generation with voltage follower buffers

 Selectable display bias configurations: static,

⁄

, or

⁄

 Wide logic power supply range: from 1.8 V to 5.5 V

 LCD and logic supplies may be separated

 Low power consumption

 400 kHz I

C-bus interface

 No external components required

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Silicon gate CMOS process

PCF8534A

Universal LCD driver for low multiplex rates

Rev. 6 — 25 July 2011 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

Summary of content (52 pages)

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PCF8534A Universal LCD driver for low multiplex rates Rev. 6 — 25 July 2011 Product data sheet 1. General description The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily cascaded for larger LCD applications.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package PCF8534AHL/1[1] Name Description Delivery form Version LQFP80 plastic low profile quad flat package; 80 leads; body 12  12  1.4 mm tape and reel SOT315-1 chip in tray PCF8534AU PCF8534AU/DA/1 wire bond die 76 bonding pads; 2.91  2.62  0.38 mm [1] Not to be used for new designs. Replacement part is PCF85134HL/1. 4. Marking Table 2.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 5.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 61 S11 62 S12 63 S13 64 S14 65 S15 66 S16 67 S17 68 S18 69 S19 70 S20 71 S21 72 S22 73 S23 74 S24 75 S25 76 S26 77 S27 78 S28 79 S29 80 S30 6.1 Pinning S31 1 60 S10 S32 2 59 S9 S33 3 58 S8 S34 4 57 S7 S35 5 56 S6 S36 6 55 S5 S37 7 54 S4 S38 8 53 S3 S39 9 52 S2 S40 10 51 S1 PCF8534AHL S41 11 50 S0 CLK 40 SCL 39 SDA 38 n.c. 37 n.c. 36 n.c. 35 n.c.
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PCF8534A NXP Semiconductors S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 11 12 13 14 15 16 17 18 19 20 21 22 23 VSS VLCD S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 9 10 A2 SA0 F 8 3 7 CLK A1 2 A0 SCL 6 1 5 SDA OSC 70 71 72 73 74 75 76 SYNC S57 S58 S59 BP0 BP1 BP2 BP3 C2 PCF8534A-1 4 64 65 66 67 68 69 VDD S51 S52 S53 S54 S55 S56 S50 S49 S48 S47 S46 C1 63 62 61 60 59 Universal LCD driver for low multiplex rates Top vie
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol S31 to S59 Product data sheet Pin SOT315-1 Wire bond die 1 to 29 44 to 72 Type Description output LCD segment output 31 to 59 BP0 to BP3 30 to 33 73 to 76 output LCD backplane output 0 to 3 n.c.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF8534A is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The display configurations possible with the PCF8534A depend on the required number of active backplane outputs.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ tr 2Cb VDD VLCD 60 segment drives SDA HOST MICROPROCESSOR/ MICROCONTROLLER LCD PANEL SCL PCF8534A 4 backplanes OSC A0 A1 A2 (up to 240 elements) SA0 VSS 001aah616 VSS Fig 5. Typical system configuration The host microcontroller maintains the 2-line I2C-bus communication channel with the PCF8534A.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates V on  RMS  D = ----------------------- = V off  RMS  2 a + 2a + n --------------------------2 a – 2a + n (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 21 bias is ---------- = 1.528 . 3 3 = 1.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Fig 6. PCF8534A Product data sheet Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 6 — 25 July 2011 © NXP B.V. 2011. All rights reserved.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 7. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534A allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 8 and Figure 9. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t)  VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t)  VBP1(t).
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 10. Tfr BP0 BP1 BP2 Sn Sn+1 Sn+2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 11.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency fclk. It equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr). 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. • In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required, the unused outputs can be left open-circuit.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates When display data is transmitted to the PCF8534A, the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives and depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in Figure 13.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates In cascaded applications each PCF8534A in the cascade must be addressed separately. Initially, the first PCF8534A is selected by sending the device-select command matching the first hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates • In the first write to the RAM, bits a7 to a0 are written. • In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6. • In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6. Depending on the method of writing to the RAM (standard or entire filling by rewriting), some elements remain unused or can be used.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 9. Blink frequencies Blink mode Operating mode ratio Blink frequency with respect to fclk (typical) Unit fclk = 1536 Hz off - blinking off Hz 1 f clk f blink = --------768 2 Hz 2 f clk f blink = -----------1536 1 Hz 3 f clk f blink = -----------3072 0.5 Hz An additional feature is for an arbitrary selection of LCD segments to blink.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 11. Mode-set command bit description Bit Symbol Value Description 7 to 4 - 1100 fixed value 3 E 2 display status 0[1] disabled (blank)[2] 1 enable LCD bias configuration[3] B 1 to 0 0[1] 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; one backplane 10 1:2 multiplex; two backplanes 11 1:3 multiplex; three backplanes 00[1] 1:4 multiplex; four backplanes [1] Default value.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 14. Bank select command bit description See Section 7.10.4 on page 22.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 8. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 16. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 8.5 I2C-bus controller The PCF8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8534A are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates R/W = 0 slave address control byte RAM/command byte S C R S 0 1 1 1 0 0 A 0 A O S 0 M A S B L S P B EXAMPLES a) transmit two bytes of RAM data S S 0 1 1 1 0 0 A 0 A 0 1 0 RAM DATA A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A A P b) transmit two command bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM date bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 RAM DATA A P mg
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8534A. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART I2C-bus access. 9.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 19. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage 2.5 - 6.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 19. Static characteristics …continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit LCD outputs Output pins BP0, BP1, BP2 and BP3 VBP voltage on pin BP Cbpl = 35 nF [4] 100 - +100 mV RBP resistance on pin BP VLCD = 5 V [5] - 1.5 10 k Csgm = 35 nF [6] 100 - +100 mV VLCD = 5 V [5] - 6.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 20. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S59 (VDD = 5 V) 0.5 V tPD(drv) 001aah618 Fig 21. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 22.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to 16 PCF8534As can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 21.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates VDD VLCD SDA 60 segment drives SCL SYNC PCF8534A CLK (2) BP0 to BP3 (open-circuit) OSC A0 A1 SA0 VSS A2 LCD PANEL VLCD VDD R≤ HOST MICROPROCESSOR/ MICROCONTROLLER tr 2Cb VDD VLCD 60 segment drives SDA SCL SYNC PCF8534A CLK 4 backplanes (1) BP0 to BP3 OSC A0 A1 A2 VSS SA0 VSS 013aaa513 (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 23.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. SYNC contact resistance Number of devices Maximum contact resistance 2 6000  3 to 5 2200  6 to 10 1200  11 to 16 700  The PCF8534A can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. Figure 22 and Figure 24 show the timing of the synchronization signals.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates If an external clock source is used, all PCF8534A in the cascade must be configured such as to receive the clock from that external source (pin OSC connected to VDD). It must be ensured that the clock tree is designed such that on all PCF8534A the clock propagation delay from the clock source to all PCF8534A in the cascade is as equal as possible since otherwise synchronization artifacts may occur.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 15. Bare die outline Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm PCF8534AU D e A 63 44 C1 C2 e 64 43 PC8534A-1(3) x 0 76 E 0 y 1 24 3 F 4 23 X 0 0.5 1 mm scale P4 P3 DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A D E e P1(1) P2(2) P3(1) P4(2) P2 0.38 2.91 2.62 0.06 0.05 0.10 0.09 0.08 P1 detail X Notes 1. Pad size 2. Passivation opening 3.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 23. Symbol PCF8534A Product data sheet Bonding pad locations Pad Coordinates[1] X (m) Y (m) Description SDA 1 1384.4 280 I2C-bus serial data input and output SCL 2 1384.4 760.5 I2C-bus serial clock input CLK 3 1384.4 945 external clock input and output VDD 4 978.7 1238 supply voltage SYNC 5 829.3 1238 cascade synchronization input and output OSC 6 714.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 23. Symbol Product data sheet Pad Coordinates[1] X (m) Y (m) S28 41 1384.4 621.6 S29 42 1384.4 701.6 S30 43 1384.4 781.6 S31 44 896.5 1239.4 S32 45 816.5 1239.4 S33 46 736.5 1239.4 S34 47 576.5 1239.4 S35 48 496.5 1239.4 S36 49 416.5 1239.4 S37 50 336.5 1239.4 S38 51 256.5 1239.4 S39 52 176.5 1239.4 S40 53 96.5 1239.4 S41 54 16.5 1239.4 S42 55 63.5 1239.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates REF REF C1 C2 REF F 001aai649 Fig 27. Alignment marks Table 24. Alignment mark locations [1] Symbol X (m) Y (m) C1 1387 1190 C2 1335 1242 F 1345 1173 [1] All coordinates are referenced in m to the center of the die (see Figure 26). 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 17. Packing information A 1.1 2.1 1.2 2.2 C x.1 3.1 D 1.3 F B 1.y y E x 001aai625 Fig 28. Tray details for PCF8534AU/DA/1 PC8534A-1 001aai650 Fig 29. Tray alignment for PCF8534AU/DA/1 PCF8534A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 25 July 2011 © NXP B.V. 2011. All rights reserved.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 25. Tray dimensions Symbol Description Value A pocket pitch in x direction 5.5 mm B pocket pitch in y direction 4.9 mm C pocket width in x direction 3.08 mm D pocket width in y direction 2.79 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm N number of pockets, x direction 8 M number of pockets, y direction 9 18.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 28.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 20.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
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PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.