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Product data sheet Rev. 6 — 25 July 2011 17 of 52

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency

clk

. It equals either the built-in oscillator frequency f

osc

or the external clock frequency

clk(ext)

. The clock frequency f

clk

determines the LCD frame frequency (f

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V

. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8534A in the system.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V

Remark: A clock signal must always be supplied to the device. Removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF8534A timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF8534A in the system is

maintained by the synchronization signal at pin SYNC

. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

clock.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which should be

connected directly to the LCD. The segment output signals are generated based on the

multiplexed backplane signals and with data resident in the display register. When less

than 60 segment outputs are required, the unused segment outputs must be left

open-circuit.

Table 6. LCD frame frequencies

Operating mode ratio Frame frequency with respect to f

clk

(typical) Unit

clk

= 1536 Hz

64 Hz

clk

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