User's Manual

Mobile WiMAX RAS SPI-2L10 System Description/Ed.00

4-27

4.3 Network Synchronization Message Flow

The M2DA-A can receive synchronization signals via the GPS or IEEE 1588 master.

In the SPI-2L10, the reference clocks output from the UCCM-P, which is a PS Receiver

(GPSR), is supplied to each device by the clock distribution block.

There are two types of reference clocks output from the GPSR, 10 MHz and PP2S.

The clock distribution block consists of the CPLD, PLL and FPGA, and converts the

signals received from the GPSR into the clocks necessary for each device.

In addition, the reference clocks output from the TSCM-I, which is an IEEE 1588 slave

board, is regenerated as the clocks necessary for each block in the M2DA-A and distributed

to them. These clocks are used to maintain internal synchronization in the SPI-2L10 and

operate the system.

Figure 4.18 Network Synchronization Flow of SPI-2L10

M2RU-2W M2DA-A

UCCM-P

PLL

CPU

CPRI

I/F

CPLD

PLL

CPRI

FPGA

GPS ANT.

GPS

Signal

PP2S

10 MHz

TOD

40 kHz

61.44 MHz

PP2S

80 ms

56 MHz

TOD

1.2288 Gbps

TSCM-I

PP2S

25 MHz

TOD

Optic B/H Port

Eth.SW

From

1588 Master.