User Manual

CDMA PicoBTSTM Hardware Description Page 11
2.2.1.4 Reliability
The PMCC is designed so that no single point failure of
critical components will result in more than 50% reduction in
capacity. The one exception to this rule is the interface to the
external T1 backhaul line interface. At a minimum, the PMCC
incorporates redundant, electrically isolated controller
processors and application memory. A redundancy controller
failure does not result in the loss of processor access to
memory or the T1 interface to the BSC.
2.2.2 PicoBTS
TM
base station channel card (PCC)
The PMU contains four PCCs which perform channel encoding
and decoding. This configuration ensures that a PCC failure
does not reduce PicoBTS capacity below 50%.
Each PCC provides 16 channel elements, arranged in two sets
of 8 channels. A control digital signal processor (CDSP)
controls each set of 8 channel elements. Each channel element
can perform any transmit or receive channel function under
software control.
2.2.3 PMU transmit and receive interface card (TRIC)
The TRIC provides digital conversion and analog processing
for CDMA baseband signals in the transmit and receive paths.
2.2.3.1 TRIC functions
The TRIC monitors the level and balance of the transmit I and
Q signals for each sector. Any deviations from allowed ranges
are reported as alarms to the PMCC. The TRIC also monitors
signal gain in the receive signal and reports deviations from
allowedrangesasalarms.
In addition, the TRIC is the distribution matrix for CDMA
channels between the PRUs and the channel cards.
The TRIC reports all alarm information, performance data, and
fault data to the PMCC.