Product specifications

ManualsBrandsSamsung ManualsComputer equipmentAlphaPC 164UX

AlphaPC 164UX/BX Motherboard

Technical Reference Manual

Preliminary

Summary of content (121 pages)

PAGE 1
AlphaPC 164UX/BX Motherboard Technical Reference Manual Preliminary
PAGE 2
Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
PAGE 3
Contents Preface 1 Introduction to the AlphaPC 164UX Motherboard 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.2 1.2.1 1.3 2 System Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Semiconductor 21174 Core Logic Chip . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L3 Bcache Subsystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
2.5.10 2.5.11 2.5.12 2.5.13 2.5.14 2.5.15 2.5.16 2.5.17 2.5.18 2.5.19 3 AlphaPC 164UX Bcache Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Semiconductor 21174 Core Logic Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 21174 Chip Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Devices . . . . . . . . .
PAGE 5
Power and Environmental Requirements 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 A 5–1 5–1 5–2 5–2 5–3 5–4 5–5 System Address Space A.1 A.2 A.3 A.3.1 A.4 A.4.1 A.5 A.6 A.7 A.7.1 A.7.2 A.8 A.8.1 A.8.2 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.15.1 A.15.2 A.16 A.16.1 A.16.2 B Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Parameters . . .
PAGE 6
B.4 C Support, Products, and Documentation Index vi Enclosure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
Figures 1–1 2–1 2–2 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 4–1 5–1 5–2 5–3 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 A–17 A–18 A–19 A–20 A–21 A–22 A–23 A–24 vii AlphaPC 164UX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164UX Jumper/Connector Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164UX Configuration Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164UX L3 Bcache Array . . .
PAGE 8
UXTables 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 3–1 3–2 3–3 5–1 5–2 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 B–1 B–2 B–3 B–4 B–5 AlphaPC 164UX SDRAM Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164UX Jumper/Connector List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
Preface Overview This manual describes the DIGITAL AlphaPC 164UX/BX motherboard, a module for computing systems based on the Samsung Alpha 21164 microprocessor and the Digital Semiconductor 21174 core logic chip. N Difference between AlphaPC 164UX and 164BX • AlphaPC 164UX motherboard has the Ethernet LAN Controller and Ultra Wide SCSI Controller which are not on AlphaPC 164BX motherboard. • The size of AlphaPC 164BX motherboard’s L3 cache is 2MB.
PAGE 10
Manual Organization As outlined on the next page, this manual includes the following chapters, appendixes, and an index. x • Chapter 1, Introduction to the AlphaPC 164UX motherboard, is an overview of the AlphaPC 164UX motherboard, including its components, features, and uses. • Chapter 2, System Configuration and Connectors, describes the user-environment configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations.
PAGE 11
Conventions This section defines product-specific terminology, abbreviations, and other conventions used throughout this manual. Abbreviations • Register Access The following list describes the register bit and field abbreviations: Bit/Field Abbreviation Description RO (read only) RW (read/write) WO (write only) • Bits and fields specified as RO can be read but not written. Bits and fields specified as RW can be read and written. Bits and fields specified as WO can be written but not read.
PAGE 12
Caution Cautions indicate potential damage to equipment, software, or data. Data Field Size The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword. Data Units The following data-unit terminology is used throughout this manual.
PAGE 13
Memory figures have addresses starting at the top and increasing toward the bottom. Schematic References Logic schematics are included in the AlphaPC 164UX design package. In this manual, references to schematic pages are printed in italics. For example, the following specifies schematic page 26: “. . . the ethernet controller (pc164ux.26) provide . . .” Signal Names All signal names are printed in boldface type.
PAGE 14
is accessible to the process in its current access mode. UNPREDICTABLE results may be unchanged from their previous values. Operations that produce UNPREDICTABLE results might also produce exceptions. – An occurrence specified as UNPREDICTABLE may or may not happen based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and must not constitute a security hole.
PAGE 15
1 Introduction to the AlphaPC 164UX Motherboard This chapter provides an overview of AlphaPC 164UX motherboard, including its components, features, and uses. The motherboard is a module for computing systems based on the Digital Semiconductor 21174 core logic chip. The AlphaPC 164UX provides a single-board hardware and software development platform for the design, integration, and analysis of supporting logic and subsystems.
PAGE 16
System Components and Features Figure 1–1 AlphaPC 164UX Functional Block Diagram 18 Index Control Alpha 21164 Microprocessor 2/4MB L3 Bcache Tag Data 12 Pdata 128 Pecc 16 128-Bit Data Data Switches (X5) 168-Pin Unbuffered Control Address 36 SDRAM DIMM Sockets (X6) DECchip 21174-CA Control, I/O Interface, and Address Commands Address/Control Primary PCI Bus Flash ROM PCI-to-PCI Bridge PCI-to-ISA Bridge Ethernet Controller 1 Dedicated 64-Bit PCI Slot 1 Dedicated ISA Slot 4 Devices Seco
PAGE 17
System Components and Features 1.1.1 Digital Semiconductor 21174 Core Logic Chip The Alpha 21164 microprocessor is supported by the 21174 core logic chip, which provides an interface between three units—memory, the PCI bus, and the 21164. This core logic chip is the interface between the 21164 microprocessor, main memory (addressing and control), and the PCI bus. Five Data switches provide the memory interface data path.
PAGE 18
System Components and Features Table 1–1 AlphaPC 164UX SDRAM Memory Configurations Bank 1 Bank 2 Total Memory U3 U4 U5 U6 192MB 64MB 64MB 32MB 32MB 224MB 64MB 64MB 32MB 256MB 64MB 64MB 64MB 64MB 128MB 128MB 288MB 128MB 320MB U7 U8 32MB 16MB 16MB 32MB 32MB 32MB 32MB 64MB 64MB 128MB 16MB 16MB 64MB 64MB 64MB 64MB 32MB 32MB 128MB 128MB 16MB 16MB 16MB 16MB 128MB 128MB 32MB 32MB 352MB 128MB 128MB 32MB 32MB 16MB 16MB 384MB 64MB 64MB 64MB 64MB 64M
PAGE 19
System Components and Features Table 1–1 AlphaPC 164UX SDRAM Memory Configurations Total Memory Bank 0 Bank 1 (Sheet 3 of 3) Bank 2 U3 U4 U5 U6 U7 U8 256MB 256MB 32MB 32MB 32MB 32MB 256MB 256MB 64MB 64MB 672MB 256MB 256MB 64MB 64MB 16MB 16MB 704MB 256MB 256MB 64MB 64MB 32MB 32MB 768MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 64MB 64MB 64MB 64MB 256MB 256MB 128MB 128MB 800MB 256MB 256MB 128MB 128MB 16MB 16MB 832MB 256MB 256MB 128MB 128MB
PAGE 20
System Components and Features 1.1.4 PCI Interface Overview The AlphaPC 164UX PCI interface is the main I/O bus for the majority of functions (SCSI interface, graphics accelerator, and so on). The PCI interface has a 33-MHz data transfer rate. An onboard PCI-to-ISA bridge is provided through an Intel 82371SB (SIO) chip.An onboard PCI-to-PCI bridge is provided through an DEC 21052 chip.The AlphaPC 164UX includes advanced features,Such as :six PCI slots;on-board Ultra-Wide SCSI; on-board 10/100 Mbs Ethernet.
PAGE 21
Software Support • AMD PALLV22V1015JC for clock controller. 1.2 Software Support The support elements described in this section are either included with the AlphaPC 164UX or are available separately. 1.2.1 ARCSBIOS Windows NT Firmware The AlphaPC 164UX motherboard ships with ARCSBIOS firmware and online documentation that describes how to configure the firmware for Windows NT. This firmware initializes the system and enables you to install and boot the Windows NT operating system.
PAGE 22
2 System Configuration and Connectors This chapter describes the AlphaPC 164UX configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. The AlphaPC 164UX uses jumpers to implement configuration parameters such as system speed and boot parameters. These jumpers must be configured for the user’s environment. Onboard connectors are provided for the I/O interfaces, DIMMs, and serial and parallel peripheral ports.
PAGE 23
Figure 2–1 AlphaPC 164UX Jumper/Connector Location J33 J24 J10 J22 Blk Yellow Red wire wire wire J21 J16 J7 GND +12 FOK J15 J6 J28 J5 J2 J30 J36 J29 J23 J37 J31 J17 J34 U55 J12 J25 J35 J13 Pwr LED IDE LED Pwr Switch Reset Switch SCSI LED U8 2–2 U7 System Configuration and Connectors U6 U5 U4 U3 J18
PAGE 24
AlphaPC 164UX Jumper Configuration Table 2–1 AlphaPC 164UX Jumper/Connector List Item No.
PAGE 25
Figure 2–2 AlphaPC 164UX Configuration Jumpers J28 System Configuration Jumpers Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 Option 10 Option 11 Option 12 Option 13 Option 14 Option 15 Option 16 Frequency 300 MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 566 MHz 600 MHz 633 MHz 666 MHz 700 MHz 733 MHz 766 MHz 800 MHz Option1 Option2 Option3 Option4 In In In In Out In In In In Out In In Out Out In In In In Out In Out In Out In In Out Out In Out Out Out In
PAGE 26
CPU Speed Selection (Option 1,2,3, &4) 2.2 CPU Speed Selection (Option 1,2,3, &4) The clock synthesizer makes it possible to change the frequency of the microprocessor’s clock input without having to change the clock crystal. Simply set the speed jumpers to adjust the frequency of the microprocessor’s clock. These speed jumpers are located at J28-1/2 (Option 1), J28-3/4 (Option 2), J28-5/6 (Option 3), and J28-7/8 (Option 4). These four jumpers set speed at power-up as listed in Figure 2–2. 2.
PAGE 27
AlphaPC 164UX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Sheet 2 of 3) Pin Signal Pin Signal Pin Signal Pin Signal A9 A13 A17 A21 A25 A29 A33 A37 A41 A45 A49 A53 A57 A61 B3 B7 B11 B15 B19 B23 B27 B31 B35 B39 B43 B47 B51 B55 B59 — Gnd GNT# +3V AD<24> AD<20> +3V STOP# SBO# +3V AD<09> +3V AD<02> Vdd Gnd INTB PRSNT2# Gnd Vdd AD<27> AD<23> +3V IRDY# LOCK# +3V AD<12> Not used AD<05> Vdd A10 A14 A18 A22 A26 A30 A34 A38 A42 A46 A50 A54 A58 A62 B4 B8 B12 B16 B20 B24 B28 B32 B36 B40 B44 B48 B
PAGE 28
AlphaPC 164UX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Sheet 3 of 3) Pin Signal Pin Signal Pin Signal Pin Signal A83 A87 A91 B63 B67 B71 B75 B79 B83 B87 B91 D<42> Gnd D<32> — Gnd D<59> D<53> Vdd D<43> D<37> Gnd A84 A88 A92 B64 B68 B72 B76 B80 B84 B88 B92 Vdd D<36> — Gnd D<63> D<57> Gnd D<47> D<41> Vdd — A85 A89 A93 B65 B69 B73 B77 B81 B85 B89 B93 D<40> D<34> Gnd C/BE#<6> D<61> Gnd D<51> D<45> Gnd D<35> — A86 A90 A94 B66 B70 B74 B78 B82 B86 B90 B94 D<38> Gnd — C/BE#<4> Vdd D<5
PAGE 29
AlphaPC 164UX Connector Pinouts 2.5.2 ISA Expansion Bus Connector Pinouts Table 2–3 shows the ISA expansion bus connector pinouts.
PAGE 30
AlphaPC 164UX Connector Pinouts 2.5.3 SDRAM DIMM Connector Pinouts Table 2–4 shows the SDRAM DIMM connector pinouts. Table 2–4 SDRAM DIMM Connector Pinouts (U3 through U8) 1 (Sheet 1 of 2) Pin Signal Pin Signal Pin Signal Pin Signal 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 Gnd DQ3 DQ6 DQ9 DQ13 CB0 NC DQMB1 A0 A8 3.3V S2 3.3V CB3 DQ18 NC DQ21 DQ24 3.
PAGE 31
AlphaPC 164UX Connector Pinouts Table 2–4 SDRAM DIMM Connector Pinouts (U3 through U8) 1 Pin 125 129 133 137 141 145 149 153 157 161 165 Signal CK1 S3 3.3V CB7 DQ50 NC DQ53 DQ56 3.3V DQ63 SA0 Pin 126 130 134 138 142 146 150 154 158 162 166 Signal 2 BA1 DQMB6 NC Gnd DQ51 NC DQ54 DQ57 DQ60 Gnd SA1 (Sheet 2 of 2) Pin Signal Pin Signal 127 131 135 139 143 147 151 155 159 163 167 Gnd DQMB7 NC DQ48 3.
PAGE 32
AlphaPC 164UX Connector Pinouts 2.5.5 Diskette Drive Bus Connector Pinouts Table 2–6 shows the diskette (floppy) drive bus connector pinouts.
PAGE 33
AlphaPC 164UX Connector Pinouts 2.5.7 COM1/COM2 Serial Line Connector Pinouts Table 2–8 shows the COM1/COM2 serial line connector pinouts. Table 2–8 COM1/COM2 Serial Line Connector Pinouts (J12) COM1 Pin (Top) COM1 Signal COM2 Pin (Bottom) COM2 Signal 1 2 3 4 5 6 7 8 9 DCD1 RxD1 TxD1 DTR1 SG1 DSR1 RTS1 CTS1 RI1 1 2 3 4 5 6 7 8 9 DCD2 RxD2 TxD2 DTR2 SG2 DSR2 RTS2 CTS2 RI2 2.5.8 Keyboard/Mouse Connector Pinouts Table 2–9 shows the keyboard/mouse connector pinouts.
PAGE 34
AlphaPC 164UX Connector Pinouts 2.5.9 Input Power Connector Pinouts Table 2–10 shows the input power connector pinouts. Table 2–10 Input Power Connector Pinouts (J18)1 Pin Voltage Pin Voltage Pin Voltage Pin Voltage 1 5 9 13 17 +3.3 V dc Gnd 5 V SB Gnd Gnd 2 6 10 14 18 +3.3 V dc +5 V dc +12 V dc PS_ON –5 V dc 3 7 11 15 19 Gnd Gnd +3.3 V dc Gnd +5 V dc 4 8 12 16 20 +5 V dc P_DCOK –12 V dc Gnd +5 V dc 1 This pinout is ATX-compliant. 2.5.
PAGE 35
AlphaPC 164UX Connector Pinouts 2.5.
PAGE 36
AlphaPC 164UX Connector Pinouts 2.5.13 Speaker Connector Pinouts Table 2–14 shows the speaker connector pinouts. Table 2–14 Speaker Connector Pinouts (J23) Pin Signal Name 1 2 3 4 SPKR NC VDD GND Speaker output — — — 2.5.14 Microprocessor Fan Power Connector Pinouts Table 2–15 shows the microprocessor fan power connector pinouts. Table 2–15 Microprocessor Fan Power Connector Pinouts (J35) Pin Signal Name 1 2 3 +12V FAN_OK_L GND — Fan connected — 2.5.
PAGE 37
AlphaPC 164UX Connector Pinouts 2.5.16 IDE Drive LED Connector Pinouts Table 2–17 shows the IDE drive LED connector pinouts. Table 2–17 IDE Drive LED Connector Pinouts (J29) Pin Signal Name 1 2 ACTIVITY ACTIVUTYPULLUP Hard drive active 2.5.17 Reset Switch Connector Pinouts Table 2–18 shows the reset switch connector pinouts. Table 2–18 Reset Switch Connector Pinouts (J37) Pin Signal Name 1 2 GND RSTSWITCH — Reset system 2.5.
PAGE 38
3 Functional Description This chapter describes the functional operation of the AlphaPC 164UX. The description introduces the Digital Semiconductor 21174 core logic chip and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the AlphaPC 164UX major functional components. Bus timing and protocol information found in other data sheets and reference documentation is not duplicated.
PAGE 39
AlphaPC 164UX Bcache Interface 3.1 AlphaPC 164UX Bcache Interface The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array (see Figure 3–1). The data bus (pdata<127:0>), check bus (pecc<15:0>), p_tag_dirty and p_tag_ctl_par signals are shared with the system interface.
PAGE 40
Digital Semiconductor 21174 Core Logic Chip Figure 3–2 shows the AlphaPC 164UX implementation of the 21174 core logic chip. Figure 3–2 Main Memory Interface DIMM 0 DIMM 1 21164 DIMM 2 Data Switches (X5) pdata<127:0> pecc<15:0> mdata<128:0> mecc<15:0> DIMM 3 DIMM 4 DIMM 5 pc164ux.11 pc164ux.12-14 enabledataswitch<0:2> paddr<39:4> *System Control pc164ux.
PAGE 41
Digital Semiconductor 21174 Core Logic Chip • Generates the clocks, row, and column addresses for the SDRAM DIMMs, as well as all of the memory control signals (*RAS,*CAS, *WE). All of the required SDRAM refresh control is contained in the 21174. • Provides all the logic to map 21164 noncacheable addresses to PCI address space, as well as all the translation logic to map PCI DMA addresses to system memory.
PAGE 42
Digital Semiconductor 21174 Core Logic Chip Figure 3–3 AlphaPC 164UX PCI Bus Devices 21174 pc164ux.8-10 Primary PCI Bus 82371SB SIO Bridge pc164ux.28 21143 Ethernet Controller 21052 PCI to PCI Bridge pc164ux.26 pc164ux.19 ISA Bus PCI64 Slot 0 J2 Secondary PCI Bus 53C875 SCSI Controller Bus pc164ux.
PAGE 43
Digital Semiconductor 21174 Core Logic Chip The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the 21174 chip. It generates the required 32-bit PCI address for 21164 I/O accesses directed to the PCI. It also accepts 64-bit double address cycles and 32-bit single address cycles. However, the 64-bit address support is subject to some constraints. Refer to Appendix A for more information on 64-bit addressing constraints. 3.2.
PAGE 44
Digital Semiconductor 21174 Core Logic Chip • Supports PCI and CardBus interfaces • Supports an unlimited PCI burst • Supports PCI clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz • Supports automatic loading of subvendor ID and CardBus card information structure (CIS) pointer from serial ROM to configuration registers • Supports full-duplex operation on both MII/SYM and 10BASE-T ports • Provides MicroWire interface for serial ROM (1K and 4K EEPROM)
PAGE 45
ISA Bus Devices 3.2.7 PCI Expansion Slots Six dedicated PCI expansion slots are provided on the AlphaPC 164UX. This allows the system user to add additional 32-bit or 64-bit PCI options. While both the 32-bit and the 64-bit slots use the standard 5-V PCI connector and pinout, +3.3 V is supplied for those boards that require it. The SIO chip provides the interface to the ISA expansion I/O bus. 3.
PAGE 46
ISA Bus Devices 3.3.1 Combination Controller The AlphaPC 164UX uses the Standard Microsystems Corporation FDC37C666 Super I/O combination controller chip (see Figure 3–4). It is packaged in a 100-pin QFP configuration. The chip provides the following ISA peripheral functions: • Diskette controller–Software compatible to the Intel N82077 FDC.
PAGE 47
Flash ROM Address Map 3.3.2 XD Bus Device The AlphaPC 164UX XD bus drives a NVRAM,RTC,and KBDC devices. 3.3.3 ISA Expansion Slots One ISA expansion slot is provided for plug-in ISA peripheral (J10). 3.3.4 ISA I/O Address Map Table 3–1 lists the AlphaPC 164UX ISA I/O space address mapping.
PAGE 48
Interrupts 3.5 Interrupts This section describes the AlphaPC 164UX interrupt logic. PCI-, ISA-, and 21174generated interrupts are described. Figure 3–5 shows the interrupt logic. The PCI-to-ISA SIO bridge chip provides the functionality of two 8259 interrupt control devices. These ISA-compatible interrupt controllers are cascaded so that 14 external and 2 internal interrupts are available. The PCI interrupt acknowledge command should be used to read the interrupt request vector from the SIO.
PAGE 49
3–12 Functional Description * pc164ux.26 Ethernet Controller pc164ux.24 SCSI Controller *scsiirq *slotNirqX pc164ux.25 Shift Register Secondary PCI Bus pc164ux.20-22 32 PCI Slots pc164ux.25 Shift Register *v3_slot0irq3 pc164ux.23 Shift Register X can vary from a to d; N can vary from 0 to 3. pc164ux.36 Shift Register *v3_slot1irqX pc164ux.23 64 PCI Slot irqchain2 pc164ux.8 Flash ROM flash_ready_irq pc164ux.25 Shift Register Primary PCI Bus Real Time Clock pc164ux.
PAGE 50
Interrupts Table 3–2 AlphaPC 164UX System Interrupts 21164 Interrupt IPL1 Suggested Usage AlphaPC 164UX Usage irq<0> 20 Corrected system error Corrected ECC error and sparse space reserved encodings detected by the 21174 irq<1> 21 — PCI and ISA interrupts irq<2> 22 Interprocessor and timer interrupts irq<3> 23 — Reserved pwr_fail_irq 30 Powerfail interrupt Reserved mchk_irq 31 System machine check interrupt SIO NMI and 21174 errors hlt_irq — Halt Reserved 1 IPL = interrupt p
PAGE 51
Interrupts Table 3–3 ISA Interrupts Interrupt Number Interrupt Source IRQ0 Internal timer IRQ1 Keyboard IRQ2 Interrupt from controller 2 IRQ3 COM2 IRQ4 COM1 IRQ5 Available IRQ6 Diskette (floppy) IRQ7 Parallel port *IRQ81 Reserved IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available IRQ14 IDE IRQ15 IDE 1 3–14 The * symbol indicates an active low signal.
PAGE 52
System Clocks 3.6 System Clocks Figure 3–6 shows the AlphaPC 164UX clock generation and distribution scheme. The AlphaPC 164UX system includes input clocks to the microprocessor as well as clock distribution for the various system memory and I/O devices. There are other miscellaneous clocks for ISA bus support. System clocking can be divided into the following three main areas: • Microprocessor input clock — The input clock runs at the operating frequency of the 21164 microprocessor.
PAGE 53
System Clocks Figure 3–6 AlphaPC 164UX System Clocks Clock Gen (Fast) TQ2061 Oscclkin 21164 Microprocessor *Oscclkin pc164ux.4 Refclkout Clock Gen (Slow) CY2907 Oscillator pc164ux.4 CY2308 PLL pc164ux.4 pc164ux.2 Sysclk DIMM0 DIMM1 buf_dramclkax2 buf_dramclkbx2 21174 DIMM2 buf_dramclkcx2 DIMM3 buf_dramclkdx2 DIMM4 buf_dramclkex2 DIMM5 buf_dramclkfx2 DMA Hack p64_clk6 pc164ux.27 p64_clk5 p64_clk4 Arbiter pc164ux.18 p64_clk3 p64_clk2 p64_clk1 82371SB p64_clk0 Bridge pc164ux.
PAGE 54
Reset and Initialization At system reset, the 21164 microprocessor’s procirq<3:0> pins are driven by the clock divisor values set by four jumpers on J28. During normal operation, these signals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164 microprocessor’s internal divider. The 21164 microprocessor produces the divided clock output signal sysclk that drives the CY2308 PLL clock-driver chip.
PAGE 55
DC Power Distribution 3.8 DC Power Distribution The AlphaPC 164UX drives its system power from a user-supplied PC power supply. The power supply must provide +12 V dc and -12 V dc, -5 V dc, +3 V dc, and +5 V dc (Vdd). The dc power is supplied through power connector J18 (pc164ux.34), as shown in Figure 3–8. Power is distributed to the board logic through dedicated power planes within the eight-layer board structure.
PAGE 56
+3.3 V Gnd -5 V +3.3-V Pull-Ups pc164ux.23 ISA Conn. +12 V -12 V +5 V (Vcc) pc164ux.34 1,2,11 3,5,7,13 15,16,17 18 4,6,19,20 12 10 Power Connector J18 pc164ux.23 PCI64 Conn. pc164ux.20-22 PCI32 Conn. Pull-Downs +5-V Pull-Ups Integrated Circuits (21174,dimm, dimm buffer, flash,sram, arbiter) Spkr pc164ux.34 Voltage Regulator +2.5V Integrated Circuits/Clocks (pci-isa,scsi,rtc, srom,multi i/o, data switch) pc164ux.26 Ethernet controller Fan pc164ux.
PAGE 57
4 Upgrading the AlphaPC 164UX For higher system speed or greater throughput, you can upgrade SDRAM memory by replacing DIMMs with those of greater size. When configuring or upgrading SDRAM, observe the following rules: • Each DIMM must be a 168-pin unbuffered version and have a frequency of 100 MHz. • All DIMMs must be of equal size if they are in the same bank. 4.
PAGE 58
Increasing Microprocessor Speed • Replace the Digital Semiconductor 21164 microprocessor with an Alpha chip that has a higher speed rating. • Reconfigure the clock divisor jumpers. 4.2.1 Preparatory Information Caution: Static-Sensitive Component – Due to the sensitive nature of electronic components to static electricity, anyone handling the microprocessor must wear a properly grounded antistatic wriststrap.
PAGE 59
Increasing Microprocessor Speed 4. If the sink/chip/fan clip is used, remove it by unhooking its ends from around the ZIF socket retainers. 5. Using a 7/16-inch socket, remove the two nuts securing the heat sink to the microprocessor studs. 6. Remove the heat sink by gently lifting it off the microprocessor. 7. Remove and discard the GRAFOIL heat conduction pad. 8. Thoroughly clean the bottom surface of the heat sink before affixing it to the new microprocessor. 9.
PAGE 60
Increasing Microprocessor Speed Figure 4–1 Fan/Heat-Sink Assembly Screw, 6-32 x 0.875 in Qty 4 Guard, Fan Fan Clip, Heat Sink/Chip/Fan Nut, Hex, 1/4-20, 2011-T3 Aluminum, 0.438 in Across Flats, Qty 2 Torque to 20 +/- 2 in-lbs Heat Sink, with Fan Mounting Holes Thermal Pad Airflow Alpha 21164 FM-06013.AI4 a. Put the GRAFOIL thermal pad in place.
PAGE 61
Increasing Microprocessor Speed b. Attach the microprocessor heat sink. The heat-sink material is clear anodized, hot-water-sealed, 6061-T6 aluminum. The nut material is 2011-T3 aluminum (this grade is critical). Perform the following steps to attach the heat sink: 1. Observe antistatic precautions. 2. Align the heat-sink holes with the threaded studs on the ceramic package. 3. Handle the heat sink by the edges and lower it onto the chip package, taking care not to damage the stud threads. 4.
PAGE 62
5 Power and Environmental Requirements 5.1 Power Requirements The AlphaPC 164UX motherboard requires a minimum of a 300 watt power supply. The power supply must be ATX-compliant. Table 5–1 Power Supply DC Current Requirements Voltage Current +3.3 Vdc,±5% +5 Vdc,±5% -5 Vdc,±5% +12 Vdc,±5% -12 Vdc,±5% 14 A 25 A 0.5 A 10 A 0.5 A Caution: Fan sensor required. The 21164 microprocessor cooling fan must have a built-in sensor that will drive a signal if the airflow stops.
PAGE 63
Physical Parameters The AlphaPC 164UX motherboard is specified to run within the environment listed in Table 5–2. Table 5–2 AlphaPC 164UX Motherboard Environmental Requirements Parameter Specification Operating Temperature Storage Temperature Relative Humidity 10°C to 40°C (50°F to 104°F) -55°C to 125°C ( -67°F to 257°F) 10% to 90% with maximum wet bulb temperature 28°C (82°F) and a minimum dew point 2°C (36°F) 11°C/hour ±2°C/hour (20°F/hour ±4°F/hour) Rate of (dry bulb) temperature change 5.
PAGE 64
Physical Parameters 5.3.2 Board Measurements and Hole Locations Figure 5–1 shows the Board Measurements and Hole Locations for the AlphaPC 164UX. Figure 5–1 Board measurement and Hole Position Diagram 9.600" .250" .400" .650" 5.550" 3.750" 12.00" .250" 3.1" Board Measurements and Hole Locations 1.
PAGE 65
Physical Parameters 5.3.3 Board Vertical Clearance Figure 5–2 shows the Board Vertical Clearance for the AlphaPC 164UX. Figure 5–2 Board Vertical Clearance Diagram 0.5" 1.0" 2.5" 1.5" 0.5" Vertical Clearance Requirements 5–4 Power and Environmental Requirements 1.0" 1.
PAGE 66
Physical Parameters 5.3.4 ATX I/O Shield Requirements Figure 5–3 shows the ATX I/O shield dimensions for the AlphaPC 164UX. Figure 5–3 ATX I/O Shield Dimensions Standard 9 pin DSUB connector cutouts with these center points 4.924 Standard 25 pin DSUB connector cutout with this center point 3.454 2.436 1.60 1.774 .640 1.134 .990 .856 0.54 .256 .247 .240 Radius = .490 on both circles. Dimensions represent center of circles. .020 .150 6.
PAGE 67
A System Address Space This appendix describes the mapping of 21164 40-bit physical addresses to memory and I/O space addresses. It also describes the translation of a 21164-initiated address (addr_h<39:4>) into a PCI address (ad<63:0>) and the translation of a PCI-initiated address into a physical memory address. PCI addressing topics include dense and sparse address space and scatter-gather address translation for DMA operations. 1.
PAGE 68
Address Map Table A–1 Physical Address Map (Byte/Word Mode Disabled) 21164 Address1 Size (GB) (Sheet 2 of 2) Selection 87.2000.0000 – 87.3FFF.FFFF 0.50 PCI special/interrupt acknowledge 87.4000.0000 – 87.4FFF.FFFF 0.25 21174 main CSRs 87.5000.0000 – 87.5FFF.FFFF 0.25 21174 memory control CSRs 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.
PAGE 69
Address Map Table A–2 Physical Address Map (Byte/Word Mode Enabled) 21164 Address Size (GB) (Sheet 2 of 2) Selection 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.25 21174 power management CSRs 87.A000.0000 – 87.AFFF.FFFF 0.25 21174 interrupt control CSRs 87.B000.0000 – 87.BFFF.FFFF 0.25 Reserved 88.0000.0000 – 88.FFFF.FFFF 4.
PAGE 70
Address Map The 21164 address space is divided into two regions using physical address <39>: • 0 – 21164 access is to the cached memory space. • 1 – 21164 access is to noncached space. This noncached space is used to access memory-mapped I/O devices. Mailboxes are not supported. The noncached space contains the CSRs, noncached memory space (for diagnostics), and the PCI address space.
PAGE 71
Address Map Figure 1–1 Address Space Overview 21164 Environment Main System Memory PCI Memory Space PCI Window PCI Device 21164 PCI Device PCI I/O Space CSRs PCI Configuration Space LJ-05395.AI4 DMA access to the system memory is achieved using windows in one of the following three ways: • Directly, using the “Monster Window” with dual-address cycles (DAC), where ad<33:0> equals addr_h<33:0>. • Directly-mapped, by concatenating an offset to a portion of the PCI address.
PAGE 72
PCI Address Space Figure 1–2 Memory Remapping 21164 CPU Cached Memory Space (8GB) PCI Memory Space 8KB Page PCI Window Direct Map PCI Window Scatter-Gather Map LJ-05396.AI4 1.2 PCI Address Space The system generates 32-bit PCI addresses but accepts both 64-bit address (DAC1) cycles and 32-bit PCI address (SAC2) cycles. Accessing main memory is as follows: • Window 4, the “Monster Window,” provides full access to main memory. It is accessed by DAC only with ad<40> equal to 1.
PAGE 73
21164 Address Space 1.3 21164 Address Space Figure 1–3 shows an overview of the 21164 address space. Figure 1–4 shows how the 21164 address map translates to the PCI address space and how PCI devices access the 21164 memory space using DMA transactions. The PCI memory space is double mapped via dense and sparse space. The 21164 I/O address map has the following characteristics: • Provides 4GB of dense1 address space to completely map the 32-bit PCI memory space.
PAGE 74
21164 Address Space Figure 1–3 21164 Address Space Configuration 21164 Memory Space Cached Memory Scatter-Gather or Direct Translation PCI Windows Reserved PCI Memory Space PCI Memory Dense Space PCI I/O Space PCI Memory Sparse Space PCI I/O Space 21164 Programmed I/O DMA Read/Write LJ-05397.
PAGE 75
21164 Address Space Figure 1–4 21164 and DMA Read and Write Transactions 39 38 37 36 35 34 33 32 31 30 Size 00 Physical Address 0 000XX 00.0000.0000 8GB Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 0=Cached Memory Space 1=Noncached I/O Space 00XXX 7F.FFFF.FFFF 80.0000.0000 0100X 83.FFFF.FFFF 84.0000.0000 01010 84.FFFF.FFFF 85.0000.0000 01011 85.8000.0000 0110X 86.0000.0000 PCI Memory Sparse Space 704MB Maximum PCI I/O Sparse Space — 64MB PCI Memory Dense Space — 4GB 0111X 86.FFFF.
PAGE 76
21164 Address Space A.3.1 System Address Map Figure 1–5 shows the following system address regions: • Main memory address space contains 8GB. All transactions contain 64 bytes, are cache-block aligned, and are placed in cache by the 21164. Both Istream and Dstream transactions access this address space. • PCI sparse-space memory region 1 contains 512MB. Noncached 21164 read/write transactions are allowed, including byte, word, tribyte, longword (LW), and quadword (QW) types.
PAGE 77
21164 Address Space Figure 1–5 System Address Map Main Memory — 8GB 39 38 35 34 33 4 3 0 Memory Address 0 0 0 0 0 0 PCI Sparse Memory Space — 512MB Region 1 39 38 35 34 33 7 6 PCI Memory Address <28:2> 1 0 X 0 0 0 3 2 0 Size 0 0 0 PCI Sparse Memory Space — 128MB Region 2 39 38 7 6 35 34 33 32 31 PCI Memory Address <26:2> 1 0 X 0 0 1 0 0 3 2 1 0 Size 0 0 0 PCI Sparse Memory Space — 64MB Region 3 39 38 35 34 33 32 31 30 7 6 PCI Memory Address <25:2> 1 0 X 0 0 1 0 1 0 3 2 1 0 Size
PAGE 78
21164 Byte/Word PCI Space Figure 1–6 21174 CSR Space PCI Configuration Space 39 38 35 34 33 32 31 1 0 X 0 0 1 1 1 CPU Address 31 30 29 28 28 27 7 6 CSR Space Size (GB) Address Size 0 0 0 Contents 0 0 0 0.5 PCI Configuration Space 0 0 1 0.5 PCI IACK/Special Cycle 0 1 0 0 0.25 21174 Main CSRs 0 1 0 1 0.25 Main Memory Control CSRs 0 1 1 0 0.25 21174 Address Translation 0 1 1 1 0.25 Reserved 2.00 Miscellaneous 1 3 2 1 0 FM-06062.AI4 1.
PAGE 79
21164 Byte/Word PCI Space Figure 1–7 Byte/Word PCI Space PCI Memory Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 0 0 2 1 0 PCI Memory Address <31:2> 0 0 PCI I/O Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 0 1 0 PCI I/O Address PCI Type 0 Configuration Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 1 0 2 1 0 PCI Configuration Address <31:2> 0 0 PCI Type 1 Configuration Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 1 1 2 1 0 PCI Configuration Address <31:2> 0 1 LJ
PAGE 80
21164 Byte/Word PCI Space Table 1–3 shows noncached 21164 addresses when byte/word support is enabled. Table A–3 21164 Byte/Word Addressing Instruction addr_h <38:37> int4_valid <3> <2> <1> <0> LDQ 00 INT8 — — — LDL 01 addr_h<3:2> — Undefined — LDWU 10 addr_h<3:1> — — Undefined LDBU 11 addr_h<3:0> — — — STQ 00 INT4 Mask — — — STL 01 INT4 Mask — — — STW 10 addr_h<3:1> — — Undefined STB 11 addr_h<3:0> — — — A.4.
PAGE 81
Cacheable Memory Space 1.5 Cacheable Memory Space Cacheable memory space is located in the range 00.0000.0000 to 01.FFFF.FFFF. The 21174 recognizes the first 8GB to be in cacheable memory space. The block size is fixed at 64 bytes. Read and flush commands to the 21164 caches occur for DMA traffic. 1.6 PCI Dense Memory Space PCI dense memory address space is located in the range 86.0000.0000 to 86.FFFF.FFFF.
PAGE 82
PCI Dense Memory Space • The concept of dense space (and sparse space) is applicable only to a 21164-generated address. There is no such thing as dense space (or sparse space) for a PCI generated address. • Byte or word transactions are not possible in dense space. The minimum access granularity is a longword on write transactions and a quadword on read transactions. The maximum transfer length is 32 bytes (performed as a burst of eight longwords on the PCI).
PAGE 83
PCI Sparse Memory Space Figure 1–8 shows dense-space address generation. Figure 1–8 Dense-Space Address Generation 21164 Address 39 38 1 35 34 33 32 31 05 04 02 01 00 1 1 0 00 <31:5> int4_valid 21164 PCI Dense Memory Address 31 05 04 02 01 00 00 LJ04264A.AI4 The following list describes address generation in dense space: • addr_h<31:5> value is sent directly out on ad<31:5>. • addr_h<4:2> is not sent out by the 21164 and instead is inferred from the int4_valid<3:0>.
PAGE 84
PCI Sparse Memory Space A.7.1 Hardware Extension Register (HAE_MEM) In sparse space, addr_h<7:3> are used to encode byte enable bits, size bits and the low-order PCI address, ad<2:0>. This means that there are now five fewer address bits available to generate the PCI physical address. The system provides three sparse-space PCI memory regions and allows all three sparse-space regions to be relocated by way of bits in the HAE_MEM register. This provides software with great flexibility. A.7.
PAGE 85
PCI Sparse Memory Space • Hardware does not perform read-ahead (prefetch) transactions in sparse space because read-ahead transactions may have detrimental side effects. • Programmers are required to insert memory barrier (MB) instructions between sparse-space transactions to prevent collapsing in the 21164 write buffer. However, this is not always necessary. For example, consecutive sparse-space addresses will be separated by 32 bytes (and will not be collapsed by the 21164).
PAGE 86
PCI Sparse Memory Space Table 1–6 defines the low-order PCI sparse memory address bits. Signals addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quadword PCI address and are sent out on ad<25:3>. Table 1–6 PCI Memory Sparse-Space Read/Write Encodings Size addr_h<4:3> Byte Word4 00 01 Byte Offset addr_h <6:5> ad<2:0> Data-In Register PCI Byte Byte Lanes Enable1 63.....32 31.......
PAGE 87
PCI Sparse Memory Space The high-order ad<31:26> are obtained from either the hardware extension register (HAE_MEM) or the 21164 address depending on sparse-space regions, as shown in Table 1–7. See the Digital Semiconductor 21174 Core Logic Chip Technical Reference Manual for more information about the 21174 HAE_MEM CSR. Table 1–7 PCI Address Mapping 21164 Address Region ad <31> <30> <29> <28> <27> <26> CPU<32> CPU<31> 80.0000.0000 to 83.FFFF.
PAGE 88
PCI Sparse Memory Space Figure 1–10 shows the mapping for region 2. Figure 1–10 PCI Memory Sparse-Space Address Generation – Region 2 21164 Address 35 34 33 32 31 39 38 SBZ 1 1 0 0 08 07 06 05 04 03 02 00 PCI QW Address int4_valid 21164 HAE_MEM CSR 31 16 15 11 10 00 43 31 27 26 Length in Bytes Byte Offset 03 02 01 00 0 0 PCI Address LJ-04266.AI4 Figure 1–11 shows the mapping for region 3.
PAGE 89
PCI Sparse I/O Space 1.8 PCI Sparse I/O Space The PCI sparse I/O space is divided into two regions — region A and region B. Region A addresses the lower 32MB of PCI I/O space and is never relocated. This region will be used to address the (E)ISA devices. Region B is used to address a further 32MB of PCI I/O space and is relocatable using the HAE_IO register. A.8.
PAGE 90
PCI Sparse I/O Space Table 1–8 contains the PCI sparse I/O space read/write encodings. Table 1–8 PCI Sparse I/O Space Read/Write Encodings Size addr_h<4:3> Byte Word 00 3 01 Byte Offset addr_h <6:5> 21164 Instruction Allowed Data-In Register Byte Lanes 63.....32 31.......
PAGE 91
PCI Sparse I/O Space Figure 1–12 PCI Sparse I/O Space Address Translation (Region A, Lower 32MB) 21164 Address 35 34 33 32 31 30 29 39 38 1 SBZ 08 07 06 05 04 03 02 00 1 0 1 1 0 <29:8> int4_valid 21164 43 31 25 24 Length in Bytes Byte Offset 03 02 01 00 0 0 0 0 0 0 0 0 0 PCI Address LJ-04268.
PAGE 92
PCI Configuration Space 1.9 PCI Configuration Space The PCI configuration space is located in the range 87.0000.0000 to 87.1FFF.FFFF. Software is advised to clear PYXIS_CTRL when probing for PCI devices by way of configuration space read transactions. This will prevent the 21174 from generating an ECC error if no device responds to the configuration cycle (and random data is picked up on the PCI bus).
PAGE 93
PCI Configuration Space Figure 1–14 PCI Configuration Space Definition (Sparse) CPU Address 39 38 1 35 34 MBZ 32 31 29 28 21 20 16 15 13 12 07 06 05 04 03 02 00 1 1 1 0 0 0 Length Byte Offset CFG<1:0> Type 0 PCI Configuration Address Type 1 PCI Configuration Address 31 11 10 IDSEL 31 27 26 Function 24 23 0 0 0 0 0 0 0 0 08 07 16 15 Bus 11 10 Device 02 01 00 Register 08 07 Function 0 0 02 01 00 Register 0 1 LJ04270A.
PAGE 94
PCI Configuration Space Peripherals are selected during a PCI configuration cycle if the following three conditions are met: 1. Their IDSEL pin is asserted. 2. The PCI bus command indicates a configuration read or write. 3. Address bits <1:0> are 00. Address bits <7:2> select a Dword (longword) register in the peripheral’s 256-byte configuration address space. Transactions can use byte masks.
PAGE 95
PCI Configuration Space Note: If a quadword access is specified for the configuration cycle, then the least significant bit of the register number field (such as ad<2>) must be zero. Quadword transactions must access quadword aligned registers. If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is, a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-toPCI bridge.
PAGE 96
PCI Configuration Space archically behind it. If the bus number of the configuration cycle matches the bus number of the bridge chip’s secondary PCI interface, it will accept the configuration cycle, decode it, and generate a PCI configuration cycle with ad<1:0> = 00 on its secondary PCI interface. If the bus number is within the range of bus numbers that may exist hierarchically behind its secondary PCI interface, the bridge chip passes the PCI configuration cycle on unmodified (ad<1:0> = 01).
PAGE 97
PCI Special/Interrupt Cycles 1.10 PCI Special/Interrupt Cycles PCI special/interrupt cycles are located in the range 87.2000.0000 to 87.3FFF.FFFF. The Special cycle command provides a simple message broadcasting mechanism on the PCI. The Intel processor uses this cycle to broadcast processor status; but in general it may be used for logical sideband signaling between PCI agents. The special cycle contains no explicit destination address, but is broadcast to all agents.
PAGE 98
PCI to Physical Memory Address The address space here is a hardware-specific variant of sparse-space encoding. For the CSRs, addr_h<27:6> specifies a longword address where addr_h<5:0> must be zero. All the 21174 registers are accessed with a LW granularity. For more specific details on the 21174 CSRs, see the Digital Semiconductor 21174 Core Logic Chip Technical Reference Manual. For the flash ROM, addr_h<30:6> defines a byte address.
PAGE 99
PCI to Physical Memory Address Table A–12 shows the PCI target window mask fields.
PAGE 100
PCI to Physical Memory Address The window base address must be on a naturally aligned boundary address depending on the size of the window1. This rule is not particularly difficult to obey, because the address space of any PCI device can be located anywhere in the PCI’s 4GB memory space, and this scheme is compatible with the PCI specification: A PCI device specifies the amount of memory space it requires via the Base registers in its configuration space.
PAGE 101
PCI to Physical Memory Address Figure 1–17 PCI DMA Addressing Example 21164 System PCI Device's DMA Memory Space 8KB Page Scatter-Gather Map 21164 Memory Space (8GB) PCI Memory Space (4GB) PCI Device 0 PCI Device 1 PCI Device 2 LJ-05402.AI4 Figure 1–18 shows the PCI window logic. The comparison logic associated with ad<63:32> is only used for DAC1 mode; and only if enabled by a bit in the window base register for window 3. This logic is only applicable to window 3.
PAGE 102
PCI to Physical Memory Address Figure 1–18 PCI Target Window Compare PCI Address 63 40 Zero Detect 32 39 Compare & Hit Logic 31 n n-1 02 20 19 Hit (Window 3 Only) Target Window Hit Logic Hit Window 3 Hit Window 2 Hit Window 1 Hit Window 0 W_DAC Window Enable (WENB) 31 n n-1 Wn_BASE DAC 31 Wn_MASK 20 XXXXX n n-1 00000000 Window 3 SG Bit Window 2 SG Bit Window 1 SG Bit Window 0 SG Bit 20 11111 LJ04273A.
PAGE 103
Direct-Mapped Addressing 1.13 Direct-Mapped Addressing The target address is translated by direct mapping or scatter-gather mapping as determined by the Wx_BASE_SG (scatter-gather) bit of the window’s PCI base register. If the Wx_BASE_SG bit is clear, the DMA address is direct mapped, and the translated address is generated by concatenating bits from the matching window’s translated base register (T_BASE) with bits from the incoming PCI address.
PAGE 104
Scatter-Gather Addressing Table A–13 Direct-Mapped PCI Target Address Translation W_MASK<31:20> Size of Window Translated Address <32:2> 0111 1111 1111 2GB Translated Base<33:31> : ad<30:2> 1111 1111 1111 4GB Translated Base<33:32> : ad<31:2> Otherwise Not supported — (Sheet 2 of 2) 1.14 Scatter-Gather Addressing If the Wx_BASE_SG bit of the PCI base register is set, then the translated address is generated by a lookup table. This table is called a scatter-gather map.
PAGE 105
Scatter-Gather Addressing Each scatter-gather map page table entry (PTE) is a quadword and has a valid bit in bit position 0, as shown in Figure 1–19. Address bit 13 is at bit position 1 of the map entry. Because the 21174 implements valid memory addresses up to 16GB, then bits <63:22> of the scatter-gather map entry must be programmed to 0. Bits <21:1> of the scatter-gather map entry are used to generate the physical page address.
PAGE 106
Scatter-Gather TLB Table A–14 Scatter-Gather Mapped PCI Target Address Translation (Sheet 2 of 2) W_MASK<31:20> Size of SG Map Table Translated Address <32:2> 0000 0001 1111 32KB Translated Base<33:15> : ad<24:13> 0000 0011 1111 64KB Translated Base<33:16> : ad<25:13> 0000 0111 1111 128KB Translated Base<33:17> : ad<26:13> 0000 1111 1111 256KB Translated Base<33:18> : ad<27:13> 0001 1111 1111 512KB Translated Base<33:19> : ad<28:13> 0011 1111 1111 1MB Translated Base<33:20> : ad<29:13>
PAGE 107
Scatter-Gather TLB Figure 1–20 Scatter-Gather Associative TLB PCI DAC Address Cycle <31:15> 8KB CPU Page Address Hit TAG V V V V V V V V V V V V V V V V DATA V V V V V V V V V V V V V V V V PCI Address<14:13> Memory Page Address<32:13> Physical Memory Dword Address PCI Address<12:2> Index LJ04276A.AI4 Each time an incoming PCI address hits in a PCI target window that has scattergather translation enabled, ad<31:15> are compared with the 32KB PCI page address in the TLB tag.
PAGE 108
Scatter-Gather TLB mapping. Both paths are indicated — the right side shows the path for a TLB hit, while the left side shows the path for a TLB miss. The scatter-gather TLB is shown in a slightly simplified, but functionally equivalent form. A.15.1 Scatter-Gather TLB Hit Process The process for a scatter-gather TLB hit is as follows: 1. The window compare logic determines if the PCI address has hit in one of the four windows, and the PCI_BASE bit determines if the scatter-gather path should be taken.
PAGE 109
Scatter-Gather TLB Figure 1–21 Scatter-Gather Map Translation 63 40 39 32 31 n n-1 20 19 02 13 12 0000000000000000000 Window Hit Offset Compare Logic 31 W_DAC n n-1 ad_h<31:13> sent to TLB for PCI window "hit." 20 XXXXX Wn_BASE DAC indicator also sent.
PAGE 110
Suggested Use of a PCI Window 1.16 Suggested Use of a PCI Window Figure 1–22 shows the PCI window assignment after power is turned on (configured by firmware), and Table A–15 lists the details. PCI window 0 was chosen for the 8MB to 16MB EISA region because this window incorporates the mem_cs_l logic. PCI window 3 was not used as it incorporates the DAC cycle logic. PCI window 1 was chosen arbitrarily for the 1GB, direct-mapped region, and PCI window 2 is not assigned.
PAGE 111
Suggested Use of a PCI Window Table A–15 lists the PCI window power-up configuration characteristics. Table A–15 PCI Window Power-Up Configuration PCI Window Assignment Size Comments 0 Scatter-gather 8MB Not used by firmware; mem_cs_l disabled 1 Direct-mapped 1GB Mapped to 0GB to 1GB of main memory 2 Disabled — — 3 Disabled — — A.16.
PAGE 112
Suggested Use of a PCI Window This mem_cs_l range in Figure 1–23 is subdivided into several portions (such as the BIOS areas) that are individually enabled/disabled using CSRs as listed here: • The MCSTOM (top of memory) register has a 2MB granularity and can be programmed to select the regions from lMB up to 512MB. • The MCSTOH (top of hole) and MCSBOH (bottom of hole) registers define a memory hole region where mem_cs_l is not selected. The granularity of the hole is 64KB.
PAGE 113
Suggested Use of a PCI Window Note: For more detail, please refer to the Intel 82378 System I/O Manual. As shown in Figure 1–24, PCI window 0 in the 21174 can be enabled to accept the mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI window hit logic simply uses the mem_cs_l signal. For example, if mem_cs_l is asserted, then a PCI window 0 hit occurs and the devsel signal is asserted on the PCI.
PAGE 114
B Supporting Products This appendix lists sources for components and accessories that are not included with the AlphaPC 164UX. B.1 Memory Dual inline memory modules (DIMMs) are available from the following sources: Samsung Semiconductor Inc. 3566 North First St.
PAGE 115
Memory Phone: 847-360-7500 Fax: 847-360-7403 Table B–2 VisionTek DIMM Part Number List Size Part Number Width ECC 16MB 64MB 128MB VT16455.0 VT164.0 VT164V6.
PAGE 116
Thermal Products DeskStation Technology - Dist. for Dense-Pac 15729 College Blvd Lenexa, KS 66219 Phone: 800-793-3375 Table B–5 Dense-Pac Microsystems DIMM Part Number List Size Part Number Width ECC 64MB 128MB 256MB DN06408x72-00 DN12816x72-00 DN25632x72-00 72bit 72bit 72bit Yes Yes Yes B.2 Thermal Products Thermal Products Components included in this heat-sink and fan solution are heat sink, GRAFOIL pad, two hex nuts, heat-sink clips, 60-mm fan, and four screws.
PAGE 117
Enclosure B.4 Enclosure An enclosure, suitable for housing the AlphaPC 164UX and its power supply, is available from: Axxion 11 B Leigh Fisher El Paso,Tx. 79906 Phone: 915-772-0360 Fax: 915-778-3200 PN: DL17 Addtronics Industrial 43263 Osgood Road Fremont, Ca 94539 Phone: 510-490-9898 Fax: 510-490-7132 PN EX-6890A California PC Products 205 Apollo Way Hollister,Ca.
PAGE 118
C Support, Products, and Documentation If you need technical support, an Alpha CPU brochure, or help deciding which documentation best meets your needs, visit the Samsung Semicondcutor World Wide Web Internet site: http://www.samsungsemi.com You can also call or e-mail to Samsung CPU Marketing Team. Please use the following information lines for support.
PAGE 119
To order the AlphaPC 164UX motherboard, contact your local distributor. The following tables list some of the semiconductor products available from Samsung Electronics.
PAGE 120
Samsung Alpha Documentation The following table lists some of the available documentation.
PAGE 121
Title Vendor PCI Local Bus Specification, Revision 2.1 PCI Multimedia Design Guide, Revision 1.0 PCI System Design Guide PCI-to-PCI Bridge Architecture Specification, Revision 1.0 PCI BIOS Specification, Revision 2.1 PCI Special Interest Group U.S. 1–800–433–5177 International 1–503–797–4207 Fax 1–503–234–6762 82420/82430 PCIset ISA and EISA Bridges (includes 82371SB) Intel Corporation Literature Sales P.O. Box 7641 Mt.