Specifications

ManualsBrandsSamsung ManualsAir CompressorAM 24A1(B1)E12

MPC8555E

Configurable Development System

Reference Manual

Supports

MPC8555E

MPC8541E

MPC8555CDSx3RM

Rev. 1, 11/2006

Summary of content (356 pages)

PAGE 1
MPC8555E Configurable Development System Reference Manual Supports MPC8555E MPC8541E MPC8555CDSx3RM Rev.
PAGE 2
PAGE 3
Contents Paragraph Number Title Page Number Contents About This Book Audience .......................................................................................................................... xiii Organization..................................................................................................................... xiii Suggested Reading........................................................................................................... xiv General Information...................
PAGE 4
Contents Paragraph Number 3.3.2.3 3.3.2.4 3.3.2.5 3.3.2.6 3.4 3.5 3.6 3.7 3.7.1 3.8 3.9 3.9.1 3.9.2 3.10 3.10.1 3.11 3.11.1 3.12 3.13 3.14 3.14.1 3.14.2 3.15 3.15.1 3.15.2 3.15.3 Page Number Title Reset Control Register (CM_RST).......................................................................... 3-6 LED Data Register................................................................................................... 3-7 PCI Control/Status Register......................................................
PAGE 5
Contents Paragraph Number 4.9 4.10 4.11 4.12 4.13 4.14 4.14.1 4.14.2 4.15 4.15.1 4.15.2 4.15.3 4.15.4 Title Page Number PCI/PCI-X...................................................................................................................... 4-13 Reset............................................................................................................................... 4-13 Exceptions............................................................................................................
PAGE 6
Contents Paragraph Number 5.11 5.11.1 5.12 5.13 5.14 Page Number Title Configuration ................................................................................................................. 5-21 Power Supply Force Header ...................................................................................... 5-23 Mechanical..................................................................................................................... 5-23 Motherboard Dimensions ...............................
PAGE 7
Contents Paragraph Number Title Page Number Appendix E CDS Carrier BOM, Rev. 1.3 Appendix F CDS Carrier Schematics, Rev. 1.3 Appendix G CDS CDC BOM Appendix H CDS CPU Schematics (CDC) Appendix I CDS I/O Board Schematics Appendix J CDS uTCOM Schematics Appendix K CDS Arcadia BOM Appendix L CDS Arcadia X3 Schematics Glossary MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 8
Contents Paragraph Number Page Number Title MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 9
Figures Figure Number Title Page Number Figures 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 4-1 4-2 4-3 4-4 4-5 4-6 4-7 Carrier Block Diagram (Configuration 1)............................................................................... 1-4 Carrier Block Diagram (Configuration 2)............................................................................... 1-5 Daughtercard Block Diagram .......................
PAGE 10
Figures Figure Number 4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 6-2 7-1 Page Number Title CDS Daughtercard Reset Architecture ................................................................................. 4-14 CDS Daughtercard I2C Architecture .................................................................................... 4-15 CDS-Compatible Arcadia Block Diagram.............................................................................. 5-3 Arcadia RapidIO Port Connections...............
PAGE 11
Tables Table Number Title Page Number Tables 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 4-1 4-2 4-3 Default Status of Processor Board (CPU Card) Switches....................................................... 2-7 Default Status of Carrier Board Switches (Configuration 1) .................................................. 2-9 Default Status of Arcadia Board Switches (Arcadia C3.n).....
PAGE 12
Tables Table Number 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 6-1 7-1 7-2 7-3 B-1 B-2 B-3 B-4 B-5 F-1 Page Number Title CDS Daughtercard Connector Overview.............................................................................. 4-11 CDC Clocks .......................................................................................................................... 4-12 CDC PCI2 IDSEL Mapping .........................
PAGE 13
About This Book The primary objective of this reference manual is to define the functionality of the MPC8555E configurable development system (CDS). It is also intended to describe in detail the configurability of the CDS through the description of individual components and their interchangeability. Included is detailed descriptions of the physical design, device architecture, and testing/debugging procedures.
PAGE 14
About This Book • • • • • • • • • • • Appendix C, “CDS Carrier BOM, Rev. 1.2” Appendix D, “CDS Carrier Schematics, Rev. 1.2” Appendix E, “CDS Carrier BOM, Rev. 1.3” Appendix F, “CDS Carrier Schematics, Rev. 1.3” Appendix G, “CDS CDC BOM” Appendix H, “CDS CPU Schematics (CDC)” Appendix I, “CDS I/O Board Schematics” Appendix J, “CDS uTCOM Schematics” Appendix K, “CDS Arcadia BOM” Appendix L, “CDS Arcadia X3 Schematics” This reference manual also includes a glossary.
PAGE 15
About This Book Table i. Glossary of Terms Term ATM CARRIER Description Asynchronous transfer mode HIP-compliant HIPcard such as CDS, Elysium, etc.
PAGE 16
About This Book MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 17
Chapter 1 Introduction 1.1 Background The configurable development system (CDS) was developed to support a wide range of Power Architecture™ processors, such as the MPC8555E and the MPC8541E. . The system is primarily a development and evaluation system, which is enhanced by its modular design, making it highly configurable. 1.2 Scope This reference manual describes the Freescale CDS development platform. It provides details on the MPC8555E CDS hardware configuration and functionality.
PAGE 18
Introduction 1.3.1 Features NOTE The CDS system can be configured to boot as MPC8555E or MPC8541E. The CDS system by default is configured as MPC8555E. To evaluate the CDS system as MPC8541E, refer to Section 2.5, “Default Switch Configuration Table,” switch-4, bit-4 on CPU card.
PAGE 19
Introduction — Supports two Ethernet ports on the carrier card at MII/GMII, and two Ethernet ports on the I/O adapter at MII/GMII, 10/100 or 1G rates (Configuration 1). NOTE In Configuration 1, Ethernet port #4 on the I/O card is not functional. — Supports all four Ethernet ports on the carrier card. MII/GMII on Ethernet ports #1 and #2. RGMII on Ethernet ports #3 and #4, 10/100 or 1G rates (Configuration 2).
PAGE 20
Introduction 1.3.2 Diagrams Figure 1-1 is a diagram of the CDS system for Configuration 1. OC12 ATM PHY OC3 ATM PHY AdTech IOCard MUX uTCOM USB Flash 10/100 #4 NVRAM Quad PHY CPU Daughtercard BUF GBit #3 DEBUG RST GBit #1 Local Clock H/S Clock GBit #2 UART PCI-X +2.5-V Power Figure 1-1. Carrier Block Diagram (Configuration 1) MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 21
Introduction Figure 1-2 is a diagram of the CDS system for Configuration 2. OC3 ATM PHY OC12 ATM PHY AdTech MUX uTCOM GBit #1 Flash GBit #2 GBit #3 BUF NVRAM Quad PHY CPU Daughtercard DEBUG GBit #4 UART Local Clock H/S Clock +2.5-V Power PCI-X Figure 1-2. Carrier Block Diagram (Configuration 2) Figure 1-3 is a diagram of a CDS daughtercard, or a CDC.
PAGE 22
Introduction MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 23
Chapter 2 Quick Start-Up Guide This chapter provides a step-by-step guide for bringing up a CDS. 2.1 Hardware List The hardware configurations consist of different board revisions which are referenced throughout this manual as Configuration 1 or Configuration 2. Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3. The configurations are: • Configuration 1 — Arcadia, Rev. 3.1 — Carrier card, Rev. 1.2 — CPU card, Rev. 1.
PAGE 24
Quick Start-Up Guide 1. Insert memory module, noting the correct KEYING orientation, and snap into the socket. See Figure 2-1. Figure 2-1. Inserting Memory Module 2. To remove the top chassis cover, stand chassis on end and remove the two top thumb screws located in back of the chassis. See Figure 2-2. Figure 2-2. Removing Chassis Thumb Screws 3. Slide top cover toward the back while lifting, and remove. See Figure 2-3. Figure 2-3.
PAGE 25
Quick Start-Up Guide 4. Remove both side covers by lifting straight up. See Figure 2-4. Figure 2-4. Removing Chassis Side Panel 5. Now lay chassis on the side with the motherboard exposed. 6. Remove PCI bracket screws. See Figure 2-5. Figure 2-5. Removing PCI Slot Bracket Screws MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 26
Quick Start-Up Guide 7. Insert carrier card assembly into the PCI Slot 1. See Figure 2-6 and Figure 2-7. NOTE The alignment pins to guide the carrier card into the proper position are on the Arcadia motherboard. Figure 2-6. Install Carrier Card into PCI Slot Figure 2-7. Guide Pin Alignment 8. Push the carrier card assembly down firmly to fully seat connectors. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 27
Quick Start-Up Guide 9. Re-install the PCI bracket screws. See Figure 2-8. Figure 2-8. Install PCI Bracket Screws 2.3 Quick Start-Up 1. Connect the CDS system to a 120-V AC power source. (For outside the U.S., a 240-V power supply must be installed in the box and connected to an AC power source.) 2. Connect the null modem serial cable between the carrier board COM1 port and the PC workstation serial port (COM1 or COM2). 3. Start up the terminal emulator program, (i.e.
PAGE 28
Quick Start-Up Guide CPU Board Revision 0.0 (0x0000) PCI1: 32 bit, 33 MHz, sync PCI2: 32 bit, 66 MHz, async I2C: ready DRAM: Initializing SDRAM: 64 MB DDR: 256 MB FLASH: 16 MB L2 cache 256KB: enabled In: serial Out: serial Err: serial Net: TSEC0: PHY is Marvell 88E1145 (1410cd4) TSEC1: PHY is Marvell 88E1145 (1410cd4) TSEC0, TSEC1 The IP address of the board is currently set to 169.254.113.
PAGE 29
Quick Start-Up Guide 10. erase ff800000 ffdfffff 11. cp.b 1000000 ff800000 1fffff 12. cp.b 2000000 ffa00000 3fffff Steps 13 to 16 are required to update the environment variables. 13. setenv bootargs root=/dev/ram rw console=ttyS1,115200 14. setenv bootcmd bootm ff800000 ffa00000 15. saveenv 16. reset 2.5 Default Switch Configuration Table The CDS system has several options for the switch settings to allow users to easily change the configuration.
PAGE 30
Quick Start-Up Guide Table 2-1. Default Status of Processor Board (CPU Card) Switches (continued) SW Bit 2 1 3 Name Core voltage 1 2 0 3 0 4 1 5 1 Note 10011 1.
PAGE 31
Quick Start-Up Guide Table 2-2.
PAGE 32
Quick Start-Up Guide Table 2-2. Default Status of Carrier Board Switches (Configuration 1) (continued) SW Bit 4 1 Name Local clock R(2:1) 2 3 Default (1 = ON) 1 Note 10 Part of 33 MHz SYSCLK 0 Local clock V(6:1) 0 4 0 5 1 6 0 7 0 8 0 001000 Part of 33 MHz SYSCLK Notes: 1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1. 2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0. b Table 2-3. Default Status of Arcadia Board Switches (Arcadia C3.
PAGE 33
Quick Start-Up Guide Table 2-3. Default Status of Arcadia Board Switches (Arcadia C3.
PAGE 34
Quick Start-Up Guide MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 35
Chapter 3 CDS Carrier Architecture This chapter describes in detail the CDS carrier system. It describes the physical layout and assembly, as well as basic and detailed system architecture. This chapter elaborates on usage and testing/debugging procedures. The CDS carrier is the backbone of the CDS system. It facilitates communication between the components as well as with outside parts through the PCI port. 3.1 Overview The following sections give the CDS board measurements and block diagram. 3.1.
PAGE 36
CDS Carrier Architecture OC3 ATM PHY OC12 ATM PHY AdTech IOCard MUX uTCOM USB Flash 10/100 #4 NVRAM Quad PHY CPU Daughtercard BUF GBit #3 DEBUG RST GBit #1 Local Clock H/S Clock GBit #2 UART PCI-X +2.5 V Power Figure 3-1. Carrier Block Diagram (Configuration 1) MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 37
CDS Carrier Architecture Figure 3-2 is a diagram of the CDS system for Configuration 2. OC3 ATM PHY OC12 ATM PHY AdTech MUX uTCOM GBit #1 Flash GBit #2 GBit #3 CPU Daughtercard BUF NVRAM Quad PHY DEBUG GBit #4 UART Local Clock H/S Clock PCI-X +2.5-V Power Figure 3-2. Carrier Block Diagram (Configuration 2) 3.2 Carrier Pinouts For a detailed pinout, including the numbering, refer to Appendix B.1, “Carrier/DaughterCard Connectors Pinout.” 3.
PAGE 38
CDS Carrier Architecture 3.3.1 System Address Map Table 3-1 describes the CDS memory map as implemented for U-Boot and Linux platform. Cadmus uses the local bus chip selects to implement the following two critical features: • Boot flash redirection • Cadmus register intervention Table 3-1.
PAGE 39
CDS Carrier Architecture 3.3.2 System Logic Registers The system logic contains several software-accessible registers which are accessed from the base address described in Section 3.3.1, “System Address Map.” Table 3-2 shows the address map of the Cadmus device. Table 3-2.
PAGE 40
CDS Carrier Architecture 3.3.2.2 General Control Register (CM_CSR) The CM_CSR register contains various control and status fields, as described below. 0 R 1 USER 2 3 -rsv- -rsv- 0 0 4 5 6 7 EPHY(4:2) LED W Reset 0 0 Offset 0 0 0 0 0x01 Figure 3-4. Reset Control Register (CM_CSR) Table 3-4. CM_CSR Field Descriptions Bits Name Description 0–1 USER Reflects the settings of the USER switches on the carrier. Software may make use of these bits; CDS does not do anything with them.
PAGE 41
CDS Carrier Architecture Table 3-5. CM_RST Field Descriptions (continued) Bits Name 6 HRESET This bit allows a device to assert HRESET to itself. As HRESET may be a level-sensitive signal (device-dependent), it is a self-resetting bit. 7 SRESET This bit allows a device to assert SRESET to itself. As SRESET may be a level-sensitive signal (device-dependent), it is a self-resetting bit. 3.3.2.
PAGE 42
CDS Carrier Architecture Table 3-7. CM_PCI Field Descriptions Bits Name Description 0 M66O If set, the M66EN signal is forced low; otherwise, the M66EN pin is three-stated and the PCI bus speed is set by the daughtercard settings and/or the PCIXCAP/PCIXCO settings. Note: It is a violation of PCI protocol to change M66EN after PCIRST has been released; the effects of this bit are system-dependent.
PAGE 43
CDS Carrier Architecture Table 3-8. CM_DMA Field Descriptions Bits Name 1 5 DMARQ0 DMARQ1 Sets the corresponding DMARQ line to the value written 2 6 DMACK0 DMACK1 Reflects the status of the corresponding DMACK line 3 7 DMADN0 DMADN1 Reflects the status of the corresponding DMADN line 3.4 Description CPM Connections The CDS carrier supports some peripherals for evaluating Ethernet and ATM interfaces for those processors which support CPM or CPM-compatible communications machines.
PAGE 44
CDS Carrier Architecture Table 3-9. CDS CPM/CE Connection Options CE/CPM Port Definition Switch FCC1 OC12 SW3–8 622 Mbps ATM PHY uTCOM UTOPIA 8 only Adtech support FCC2 OC3 SW3–7 155 Mbps ATM PHY uTCOM No UTOPIA connection No Adtech support FCC3 10/100 SW3–6 FEthernet uTCOM FCC 3 not supported on MPC8555E/41E Switch = 0 Definition Switch = 1 Definition Notes The specific CPM/CE port bits that need to be switched for each mode are listed in Table 3-10 and Table 3-11. Table 3-10.
PAGE 45
CDS Carrier Architecture Table 3-11. CPM Port Routing for FCC2 in ATM155 Mode (continued) Group Bit ATM Signal 15 14 13 12 11 10 9 8 7 6 RXADD(4:0) 5 4 3 2 1 0 PD29 PD18 PC10 PC23 PC16 RXCLAV PB29 RXCLK PC19 Because not all of the CPM signals are optionally re-routed, some of the connections sent to the uTCOM header are from the switch device, and others are from the CPM port of the processor. This is summarized in Table 3-12. Table 3-12.
PAGE 46
CDS Carrier Architecture 3.5 ATM Interfaces AdTech From Daughtercard The CDS carrier card provides two dedicated ATM ports, one at 622 Mbps and the other at 155 Mbps. The general architecture is shown in Figure 3-10. FCC1 FCC2 PM5357 622 Mbps HFBR58208M PM5384 155 Mbps HFBR5805 Figure 3-10. CDS ATM Architecture Table 3-13 describes the details of the ATM interface. Table 3-13. ATM Port Overview 3.
PAGE 47
CDS Carrier Architecture NOTE In Configuration 1, TBI, RTBI, RMII, and RGMII interface modes are not supported. In Configuration 1, Ethernet port #4 on the I/O card is not functional. In Configuration 2, RGMII is supported only on Ethernet ports #3 and #4. The fourth port is optionally extracted from the FCC3 pins on port B pins of the CPM engine as detailed in Section 3.4, “CPM Connections.” In addition to the special pins, the fourth port is only connected as a 10/100baseT port.
PAGE 48
CDS Carrier Architecture MI RJ45 + MAG Daughtercard TSEC1 Port 0 TSEC2 CIS8204 1 PHY 2 RJ45 + MAG RJ45 + MAG 3 10/100 ⊗ RJ45 + MAG EPHY_ADR[4:2] IOCard 125 MHz CADMUS Figure 3-11. CDS Ethernet Architecture (Configuration 1) MI RJ45 + MAG Daughtercard GMI/RGMII TSEC1 Port 0 GMII TSEC2 Marvell 88E1145 RGMII 10/100 1 2 3 RGMII RJ45 + MAG ⊗ RJ45 + MAG RJ45 + MAG 125 MHz Figure 3-12.
PAGE 49
CDS Carrier Architecture Table 3-15 summarizes the connections to the TSEC interface and associated PHY. Table 3-15.
PAGE 50
CDS Carrier Architecture The bus is treated as a general-purpose interface and leaves decisions such as chip select to the daughtercard. The connections and accompanying interface logic is shown in Figure 3-13. Flash #1 CLA ADDR Flash #2 CADMUS Daughtercard CS[0:7] PromJet NVRAM OTHER Logic An. PHYs uTCOM DATA Figure 3-13. CDS Local Bus Architecture Table 3-16 lists the pins of the daughtercard connector. Table 3-16.
PAGE 51
CDS Carrier Architecture Table 3-16.
PAGE 52
CDS Carrier Architecture Table 3-17. CDS Cxx Local Bus Signals (continued) Signal Name Description Notes ATM1_CS ATM PHY #1 chip select ATM622 Mbps device ATM2_CS ATM PHY #2 chip select ATM155 Mbps device ATM1X_CS AdTech PHY chip select AdTech external chip select Table 3-18 is an example of how the local bus address (LB_A(0:31)) is converted into the size-aligned address suitable for the local bus. Table 3-18. CLA Mapping LBSZ(0:1) Setting 00 (8-bit) CLA(23) = LB_A(8) CLA(22) = LB_A(9) ...
PAGE 53
CDS Carrier Architecture The CDS carrier clock resources are summarized in Table 3-19. Table 3-19. CDS Clock Requirements Summary Clock Signal Frequency Range Voltage Level Require Notes PCICLK 33/66 MHz 3.3V LVTTL SYSCLK 10–200 MHz 3.3V LVTTL PHYCLK 125 MHz 3.3V LVTTL QuadPHY on CDS main board RTC_CLK 16 MHz 3.3V LVTTL Timing base for the performance monitor PCI interface of daughtercard The overall clock architecture is shown in Figure 3-14.
PAGE 54
CDS Carrier Architecture NOTE It is not possible to disable the PCI bus when an active PCI bus is present on the motherboard; that is, there is no isolation circuitry between the processor PCI interface and the PCI edge connector, so when CDS is plugged into a PCI slot, it must be configured to be PCI enabled. Local Reset PCIRST Local Clock SYSCLK Daughtercard Connector The general PCI architecture is shown for Rev. 1.1 CDC in Figure 3-15. other PCI PCICLK PCI Edge Connector Figure 3-15.
PAGE 55
CDS Carrier Architecture daughtercard can be configured to act as a system host: accepting inbound PCI traffic and performing system enumerations. This does not mean that the CDS cannot function as the PCI host, in fact in most shipped system, the CDS will be the PCI host. Arbitration and host/agent functions are associated, but entirely separable. 3.9.2 PCI-X System Control PCIXCAP settings are determined by the daughtercard.
PAGE 56
CDS Carrier Architecture The resulting connections and notes are listed in Table 3-21. Table 3-21.
PAGE 57
CDS Carrier Architecture 3.10.1 Software Triggered Exceptions Software can trigger an IRQ9 event by writing to appropriate registers in the Dallas DS1553WP non-volatile SRAM/RTC. The following sequence is recommended: Set the WatchDog Register (offset 0x1FF7 from the LCS2* base (typically 0xFD00_0000)) to RB(1:0) = %00 (1/16 second resolution) BMB(4:0) = %00001 (minimum delay) WDS = %0 (assert IRQ9) After 1/16 of a second, the IRQ9 interrupt will be asserted.
PAGE 58
CDS Carrier Architecture Table 3-22. CDS Reset Sources Source How Asserted Type Carrier Power cycle POR_RST Remote control port High-to-low transition of RMT_POR POR_RST Remote control port High-to-low transition of RMT_RST SYS_RST Processor High-to-low transition of HRESET_REQ SYS_RST NVRAM watchdog High-to-low transition of NVRST (maskable) SYS_RST Table 3-23.
PAGE 59
CDS Carrier Architecture 2. Set the WatchDog Register (offset 0x1FF7 from the LCS2* base (typically 0xFD00_0000)) to: RB(1:0) = %00 (1/16 second resolution) BMB(4:0) = %00001 (minimum delay) WDS = %1 (assert NVRST (which will assert HRESET to the processor and other devices)). NOTE The system startup code must initialize the WatchDog timer by writing a zero to the WatchDog register.
PAGE 60
CDS Carrier Architecture Table 3-24. CDS I2C Bus Properties I2C Device I2C Device I2C Address Data Size CDC system ID EEPROM AT24C64A 0x56 (1010_110x) 8192 Remote control/configuration port PCA9557 0x1C (0011_100x) 0x1D (0011_101x) 0x1E (0011_110x) 0x1F (0011_111x) 8 Notes 1, 2 Notes: 1. CDC daughtercards may also have configuration switches, at addresses 0x18.01B. 2.
PAGE 61
CDS Carrier Architecture Table 3-25. CDS Configuration Parameters Configuration Option Config.
PAGE 62
CDS Carrier Architecture Once a particular I2C control output has been programmed, the rail-to-rail output FETs in the PCA9557 will overdrive the weaker pullup/pulldowns, granting the I2C output register direct control over the configuration logic. Note that the I2C I/O controller outputs remain constant even when HRESET is asserted.
PAGE 63
CDS Carrier Architecture Table 3-26. CDS Available Power (continued) Power Source Current Power +12 V HIP — — PCI 1A 12 W Total 1A 12 W HIP — — PCI 1A 12 W Total 1A 12 W –12 V The power budget must be compared to the two separate 5-/3.3-V rating limits (78 W + 52 W and 103 W + 77 W, respectively) to determine if the board can be operated in a non-PCI-based environment. 3.14.1 +2.5-V Power The +2.5-V power source is supplied by a switching power supply module. It supplies +2.
PAGE 64
CDS Carrier Architecture Table 3-27.
PAGE 65
CDS Carrier Architecture Table 3-28.
PAGE 66
CDS Carrier Architecture Table 3-29.
PAGE 67
CDS Carrier Architecture 3.15.2 Remote Debug Header This 2x5-pin right-angle Berg header is used for special test environments. Table 3-30 shows the pin definitions. Table 3-30. CDS Remote Header Pin Signal Definition 1 SCL I2C serial clock 2 SDA I2C serial data 3 GND System ground 4 GND System ground 5 N/C 6 N/C 7 RMT_UDE 8 N/C 9 RMT_RST Open-collector active-low reset input. Pulled up to ~3 V. 10 RMT_POR Open-collector active-low power-on reset input. Pulled up to ~3 V.
PAGE 68
CDS Carrier Architecture Table 3-32. CDS LEDs (continued) LED Label LED No. Definition L5_CLK 5 Clock active L6_MEM 6 Flash/local-bus memory active L7_MISC 7 Miscellaneous reporting Note that software can override the functions of LEDs 0–7 and replace them with user-defined activity. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 69
Chapter 4 CDS Daughtercard Architecture The following sections will cover the CDS daughtercard (CDC) design in more detail. Note that, because the daughtercard is the most interchangeable part of the CDS system, this section will be more general. Refer to the data sheets for more detail on a particular daughtercard. The CDS system supports a variety of processors, both individual and integrated devices.
PAGE 70
NVRAM Mictor HIP Power HIP P6880 P6880 FPGA AdTech ATM PHY ATM PHY Flash Mictor HFBR HFBR Flash PromJET CDS Daughtercard Architecture FCI Right QPHY Daughtercard FCI uTCOM (Rear) 335 [13.25] Quick Switch Samtec Diff FCI Left UART 130 [5.2] RJ45 RJ45 IO Module Samtec Figure 4-1. Daughtercard Placement MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 71
CDS Daughtercard Architecture The daughtercard’s large dimension allows multiple cards to be inserted into the Arcadia HIP motherboard, but it is not big enough to restrict access to the carrier communication components. The CDC dimensions are as follows: • Component height at the top: 15 mm • Component height at the bottom: 4 mm Figure 4-2 shows the placement of the processor on the daughtercard. . Right-Angle PCI 90°-Angle DIMM 102.0 [4.0] 120.0 [4.7] Heatsink/Fan P6880 18.0 130.0 [5.1] 160.0 [6.
PAGE 72
CDS Daughtercard Architecture 4.2 CDS Daughtercard (CDC) Block Diagram Figure 4-3 is a diagram of a CDS daughtercard or a CDC. Vtt DDR SDRAM DIMM DEBUG VTT Power Core Power CPU or PCI/X/Ex CPU/Bridge JTAG LBIF CFG Local Mem Header (Right) Header (Left) I2C ID Figure 4-3. Daughtercard Block Diagram This representation is only one, others can be designed for different CPUs. 4.
PAGE 73
CDS Daughtercard Architecture MDQS[8:0] MDM[8:0] MDQ[63:0] RAS CAS WE CKE[1:0] S[1:0] S[3:2] A[14:0] BA[1:0] DQS[0:8] DM[8:0] DQ[63:0] MCK[0:1] MCK[0:1] MCK[2:3] MCK[2:3] Rterm CK[0:1] CK[0:1] MSYNC_OUT MSYNC_IN MEM_RST RESET I2C_SDA I2C_SCK SDA SCL MVREF VREF CB[7:0] Rterm MECC[7:0] Vterm Resistors and Decoupling MRAS MCAS MWE MCKE[1:0] MCS[1:0] MCS[2:3] MA[14:0] MBA[1:0] Rterm DDR DIMM Rterm Processor MDBG MDEBUG VTT QS Header VREF’ VDDQ LP2995 Figure 4-4.
PAGE 74
CDS Daughtercard Architecture Table 4-1.
PAGE 75
CDS Daughtercard Architecture Table 4-1.
PAGE 76
CDS Daughtercard Architecture A 22-Ω resistor is selected to match the processor impedance to the PWB impedance, but can be trimmed or altered as necessary. After daisy-chaining the control signals, the line is extended to a 27-Ω resistor (also 1%) which connects directly to the VTT termination plane. 4.4.2 Recommended Part Numbers For performance and compatibility purposes, only the devices shown in Table 4-2 are guaranteed to work.
PAGE 77
CDS Daughtercard Architecture interface properly with the peripherals supported on the carrier. If differing access sizes are needed, LB_SIZ can be generated dynamically, however, it is typically only set to one particular size. NOTE The data bus size option only affects how the CDC and carrier provide access to Flash memory (particularly for boot code).
PAGE 78
CDS Daughtercard Architecture Table 4-3 lists the daughtercard connector pins. Table 4-3.
PAGE 79
CDS Daughtercard Architecture optional second PCI slot. There are two separate connectors to provide easier routing and vacate the area under the processor for mechanical reasons. The connectors and brief pinout are described in Table 4-4. Table 4-4.
PAGE 80
CDS Daughtercard Architecture Table 4-4. CDS Daughtercard Connector Overview (continued) Signal Group Signals Left Pin Count Right Pin Count Notes Power +12V VCC_12V 2 0 Imax = 0.9 A, Pmax = 10.8 W Power –12V VCC_12N 0 1 Imax = 0.5 A, Pmax = 5.4 W Ground GND 95 86 USB 2.0 U1_TP, U1_TN, U1_OC U2_TP, U2_TN, U2_OC 6 Subtotal 387 344 Spares 13 56 Total 400 400 Bring up to next connector size Note: The FCI connector supports 0.45 A/pin. 4.
PAGE 81
CDS Daughtercard Architecture 4.9 PCI/PCI-X The PCI/PCI-X signals from the primary PCI interface of the processor are connected to the edge connector of the CDS carrier board. In addition, some processors have a secondary PCI interface, which may operate independently of the primary PCI bus. If implemented, the optional PCI interface is connected to a PCI connector on the CDC, and is completely independent of the primary PCI interface.
PAGE 82
CDS Daughtercard Architecture A second reset (CFGRST) is optionally asserted along with HRESET. They have the same period and edge rate, but CFGRST is delayed one clock cycle. This signal is used to drive configuration data onto processor/bridge configuration pins, which in turn are sampled at the rising edge of HRESET. The daughtercard can also drive a reset to the carrier using the signal HRST_REQ, and possibly to the motherboard (this is motherboard-dependent).
PAGE 83
CDS Daughtercard Architecture Table 4-7. CDS Exception Properties CDS Signal Carrier Connection IRQ0 INTA IRQ1 INTB IRQ2 INTC IRQ3 INTD IRQ4 Reserved IRQ5 MDINT On-board QuadPHY IRQ6 ATMINT ATM PHY interrupt IRQ7 CMINT CPLD interrupt (typically DMA) IRQ8 Reserved IRQ9 PERINT NVRAM/RTC periodic interval timer IRQ10 DEBUG Debug event switch (s/w managed) Routing PCI edge connector INT(A:D) Reserved Reserved IRQ11 4.
PAGE 84
CDS Daughtercard Architecture The CDC provides the I2C resources listed in Table 4-8. Table 4-8.
PAGE 85
CDS Daughtercard Architecture Table 4-9. CDC Available Power Power Pins × Current Current Power +12 V 2 × 0.45 A 0.9 A 10.8 W Total 137.5 W The power budget must be compared to approximately 170 W available to the carrier, and to the portion of that power required for the carrier itself. 4.14.1 Processor Core Power Core power (VDD) to the processor is supplied using a switching regulator. It is capable of supplying core voltages in the range 0.925–2.0 V in 25-mV steps over the lower range (0.
PAGE 86
CDS Daughtercard Architecture ADC (Maxim MAX1037EKAT, channel 0). The resulting measurement is compared to a 2.048-V reference, and produces a value from 0 to 2048, corresponding to the current shown in Table 4-11. Table 4-11. CDC ADC Current Measurement Conversion Table CPU Current I-to-V Output Conditioned ADC Input ADC Measurement 0.0 A 0.00 V 0.0 V 0 1.0 A 0.25 V 0.1 V 100 1.0 V 1000 1.5 V 1500 2.0 V 2000 ... 10.0 A 2.50 V ... 15.0 A 3.75 V ... 20.0 A 5.
PAGE 87
CDS Daughtercard Architecture Table 4-12. CDS Daughtercard P6860 Analyzer Header Definition (continued) 4.15.2 Pin Signal A7 MSRCID[4] A9 MDVAL A10 TRIG_OUT A12 TRIG_IN A13 CLK_OUT A15 HRESET B1 MDBG(0) B3 MDBG(1) B4 MDBG(2) B6 MDBG(3) B7 MDBG(4) B9 MDBG(5) B10 MDBG(6) B12 MDBG(7) Description JTAG Header This 2x10-pin Berg header is typically used with JTAG/ICE controllers to download target code and control code execution from a remote computer.
PAGE 88
CDS Daughtercard Architecture Table 4-13. CDS JTAG Header (continued) Pin Signal Definition 13 HRST 14 KEY 15 CKSTP_O 16 GND CPU HRESET input No pin present CPU CHKSTP_OUT output Ground The connector is physically arranged as shown in Table 4-14. Other pin numbering schemes are popular, however, the correspondence between each pin and the ‘picture’ in Table 4-14 is correct, whatever the pin number may be. Table 4-14. CDS COP Header Definition 4.15.
PAGE 89
CDS Daughtercard Architecture 4.15.4 Test Points Test points are added to critical signals to aid in bringup and testing. The test point list is shown in Table 4-16. Table 4-16.
PAGE 90
CDS Daughtercard Architecture MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 91
Chapter 5 Arcadia Motherboard Architecture The following sections describe information on the Arcadia Version 3 reference platform, also referred to as Arcadia x3 or Arcadia V3.
PAGE 92
Arcadia Motherboard Architecture • — Floppy disk controller — Dual serial ports ATX motherboard form-factor Figure 5-1 shows a block diagram of the Arcadia motherboard. 5.
PAGE 93
Arcadia Motherboard Architecture HIPSlot 2 HIPSlot 1 Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 IDE/USB System I/O RealTek Ethernet PCI1 PCI3 ISO1(+Shift) PCI-X/ PCI Bridge Omni Pwr HMZD Pwr HMZD ARC System Control and PCIBoot PCI4 Clock PCI4 PCI3 PCI/PCIX 5V 33 MHz 32-Bit PrPMC PCI1 PCI 3V 33 MHz 32-Bit PCI/PCIX 3V 33–66 MHz 64-Bit Omni LVDS 0–3 GHz 40-Bit Figure 5-1. CDS-Compatible Arcadia Block Diagram In general, the CDS view of the system exposes all the hardware resource features.
PAGE 94
Arcadia Motherboard Architecture Table 5-1. Arcadia Architecture Feature Summary Bus Connections Size Theoretical Maximum Speed 40 differential pairs 3.
PAGE 95
Arcadia Motherboard Architecture . Slot 2 Slot 1 Path A Transmit Transmit Receive Receive Path B Figure 5-2. Arcadia RapidIO Port Connections 5.4.1 Parallel RapidIO Table 5-2 describes the pinout of the high-speed port connector, when the parallel RapidIO protocol is in use. This pinout is as defined by the RapidIO Trade Association TWG document, RapidIO Hardware Interoperability Platform (HIP) Specification. Table 5-2.
PAGE 96
Arcadia Motherboard Architecture 5.4.2 Serial RapidIO Table 5-3 describes the pinout of the high-speed port connector, when the parallel RapidIO protocol is in use. This pinout is as defined by the RapidIO Trade Association TWG document, RapidIO Hardware Interoperability Platform (HIP) Specification. Table 5-3.
PAGE 97
Arcadia Motherboard Architecture Table 5-4. Arcadia PCIExpress Connector Definition (continued) Pin Definition Pin Definition Pin Definition Pin Definition A8, B8 rx6 (p,n) C8, D8 rx14 (p,n) E8, F8 tx10 (n,p) G8, H8 tx2 (n,p) A9, B9 rx7 (p,n) C9, D9 rx15 (p,n) E9, F9 tx9 (n,p) G9, H9 tx1 (n,p) A10, B10 RST#, n/a C10, D10 E10, F10 tx8 (n,p) G10, H10 tx0 (n,p) Notes: 1. BG(1:10), DG(1:10), FG(1:10), and HG(1:10) are all connected to system ground. 2.
PAGE 98
Arcadia Motherboard Architecture Table 5-5. Arcadia PCIBus Name Examples PCI Signal 5.5.1 Connects to PCIA_FRAME or PCIA1_FRAME PCIBridge primary side, HIPSlot 1 (PCI Slot 2), PCI Slot 4, HIPSlot 1 (PCI Slot 5) PCIB3_FRAME PCIBridge secondary side, ARC PCI interface, PCI B isolation buffer 3 PCIB4 PCI B isolation buffer 4, Ethernet VIA PIPC PrPMC PCI Slot 6 PCI Slot 7 PCI Arbitration The Arcadia contains two separate PCI buses (separated by the PCI bridge).
PAGE 99
Arcadia Motherboard Architecture HIPSlot 2 HIPSlot 1 Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 IDE/USB System I/O RealTek Ethernet PCI1 ARC System Control and PCIBoot Pwr HMZD Pwr HMZD PCI A Omni Shifter PCI3 PCI-X/ PCI Bridge PCI4 PrPMC Clock PCI B PCI4 PCI3 PCI/PCIX 5V 33 MHz 32-Bit PCI1 PCI 3V 33 MHz 32-Bit PCI/PCIX 3V 33–66 MHz 64-Bit Omni LVDS 0–3 GHz 40-Bit Figure 5-3.
PAGE 100
Arcadia Motherboard Architecture Table 5-6. PCI Arbitration Ports (continued) Component 5.5.2 Bus Arbiter Port Primary PCI Bridge A PCIA_REQ/GNT*(0:4) 0 Slot 2 A 1 Slot 3 A 2 Slot 4 A 3 Slot 5 A 4 Notes PCI Host Mode As with all HIP systems, all components on the board are peers. That is, any one (or multiple) HIP and/or PrPMC cards can service interrupt requests. This is essential, as in some configurations, a HIP card or a PrPMC card may not be present.
PAGE 101
Arcadia Motherboard Architecture HIPSlot 2 HIPSlot 1 Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 IDE/USB System I/O RealTek Ethernet PCI A PCI1 Omni Pwr HMZD Pwr HMZD Int. Bridge ARC System Control and PCIBoot Clock PCI4 PCI3 PCI/PCIX 5V 33 MHz 32-Bit PCI3 Shifter PCI-X/ PCI Bridge PrPMC PCI4 PCI1 PCI 3V 33 MHz 32-Bit PCI/PCIX 3V 33–66 MHz 64-Bit Omni LVDS 0–3 GHz 40-Bit Figure 5-4.
PAGE 102
Arcadia Motherboard Architecture Table 5-7. Arcadia 3.
PAGE 103
Arcadia Motherboard Architecture Table 5-7. Arcadia 3.
PAGE 104
Arcadia Motherboard Architecture secondary devices if needed. Devices on the secondary interface cannot configure anything on slots 2, 3, 4, and 5. Table 5-8. PCI Configuration Addresses Bus Schematic Device Number Notes PrPMC IDSEL #1 B4 16 1 Secondary PCI bridge B3 17 2 ARC B3 18 RTK8139 Ethernet B4 21 VIA 82C686B B4 20 Slot 6 B4 22 Slot 7 B4 23 Primary PCI bridge A 28 Slot 2 A 20 Slot 3 A 21 Slot 4 A 22 Slot 5 A 24 Component Notes: 1.
PAGE 105
Arcadia Motherboard Architecture • • • 5.7 VIA SIOINT to PCIB interrupt mapping PCIA speed detection and control Optional: PCI boot for PrPMCs Clocking Arcadia provides clocks to the PCI/PCI-X slots and devices (both buses), the AGP slot, the PrPMC connector, the arbiter/system logic, and the PCI bridge. With multiple PCI domains, each domain may operate at a different frequency than the others, as shown in Figure 5-5.
PAGE 106
Arcadia Motherboard Architecture Table 5-9.
PAGE 107
Arcadia Motherboard Architecture Bridge 33 MHz PCI #2 PCI #4 MPC9855 PCI #5 M66EN PCIXCAP ARC FPGA ARC FPGA 33 MHz Bridge PrPMC MPC9109 Ethernet PSIPC Slot 6 Slot 7 ARC FPGA Figure 5-6. Arcadia Clock Architecture Arcadia uses the MPC9855 clock synthesizer to generate 33/66 MHz primary PCI clock rates; 33 MHz secondary PCI clocks are generated by a buffered version of the clock input.
PAGE 108
Arcadia Motherboard Architecture PrPMC PCI A Switch ATX PSU ARC TSI310 PCI B Clock VIA Port 92H Figure 5-7. Arcadia Reset Architecture In operation, the assertion of any the reset pushbutton switches, the power supply, or a signal from the MPMC card may initiate a system reset and cause the reset controller to drive the global reset signals low. Note that, as PCI is optional, the HIP cards do not have a reset definition.
PAGE 109
Arcadia Motherboard Architecture Table 5-10. Arcadia Slot Power Availability Power Source Current Power 5V HIP 2 × 7.8 A 78 W PCI 5A 25 W Total 20.6 A 103 W HIP 2 × 7.8 A 52 W PCI 7.6 A 25 W Total 23.2 A 77 W HIP — — PCI 0.5 A 6W Total 0.5 A 6W HIP — — PCI 0.1 A 1.2 W Total 0.1 A 1.2 W 3.3 V 12 V –12 V Note that if a RapidIO HIP card requires +12 or –12 V, it will have to tap into the PCI slot or synthesize its own power using an energy conversion device.
PAGE 110
Arcadia Motherboard Architecture Table 5-11.
PAGE 111
Arcadia Motherboard Architecture 5.11 Configuration Arcadia contains several slide-switches used to configure the board, processors(s) and chipsets for the options shown in Table 5-14. Underlined entries are the defaults, as shipped. Since the switches operate by connecting a pulled-up signal to ground, setting a switch to ON is indicated as ‘1’ in the table. All switches are oriented so that ON = 1 = UP, where UP means toward the PCI and I/O connector back panel of the ATX chassis.
PAGE 112
Arcadia Motherboard Architecture Table 5-14. Arcadia Configuration Switches (continued) Switch SW3 No.
PAGE 113
Arcadia Motherboard Architecture Table 5-14. Arcadia Configuration Switches (continued) Switch SW2 No. Option Description Default Setting Notes 1 ARC0 0/OFF: SIOINT -> PCIB3_INT0 1/ON: SIOINT -> PCIB3_INT1 0 2 ARC1 Reserved 1 3 ARC2 Reserved 1 4 G0 Switch readable on VIA GPI5 1 3 5 G1 Switch readable on VIA GPI6 1 3 6 LPCWP* 0/ON: LPC flash is write-protected 1/OFF: LPC flash is write-enabled 1 4 7 rsvd N/A 1 8 rsvd N/A 1 Notes: 1.
PAGE 114
Arcadia Motherboard Architecture 5.13 Motherboard Dimensions Arcadia is a standard 12.0 × 9.6 inch (305 × 244 cm (the specification is written in inches)) motherboard, and follows standard ATX 2.01 clearance requirements. Arcadia implements the standard set of mounting holes for chassis attachment, with the addition of ATX 2.01 mounting hole F, located near the communications port adapter as shown in Figure 5-8. 12.0 in. F 8.95 in. 9.6 in. 6.1 in. 0.9 in. 3.1 in. 4.9 in. 11.1 in. Figure 5-8.
PAGE 115
Arcadia Motherboard Architecture 5.14 Placement The general placement of components on the Arcadia motherboard is shown in Figure 5-9. 12.0 in. F RTK FPGA 0.9 in. TSI310 8.95 in, 9.6 in. 6.1 in, PrPMC VIA 3.1 in. 4.9 in. 11.1 in. Figure 5-9. Component Placement MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 116
Arcadia Motherboard Architecture MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 117
Chapter 6 CDS IOCard Architecture This chapter describes the IOCard in detail. It elaborates on the physical architecture and device connections, as well as the power management and usage. 6.1 Mechanical Properties The CDS IOCard is essentially a PCB and connector implementing a passive but high-quality, balanced connection between communications devices and the connectors.
PAGE 118
CDS IOCard Architecture The approximate placement and component sizes of the CDS IOCard are shown in Figure 6-2. 38 [1.5] RJ45 107 [4.2] RIser RJ45 USB USB 9.5 [0.375] PWR 1 in.2 1 cm2 Cutout to allow adjacent PCI slots 9.5 [0.375] Figure 6-2. CDS IOCard Physical Dimensions 6.2 IOCard Connector The IOCard uses a high-speed, high-density connector. Table 6-1 lists the pins of the daughtercard connector. Table 6-1.
PAGE 119
CDS IOCard Architecture Table 6-1. CDS IOCard Connector Details (continued) 6.3 Signal Group Signal Pin Count Spares Spares 6 Total Total 100 Notes Bring up to next connector size — IOCard Connector Pinout For a detailed pinout, including numbering, refer to Appendix B.2, “IOCard Connector Pinout.” 6.4 IO Power IO power is obtained from the carrier, which supplies +2.5- and +3.3-V power.
PAGE 120
CDS IOCard Architecture MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 121
Chapter 7 uTCOM Architecture This chapter describes the interface of the uTCOM, as well as its physical properties. The uTCOM is an adaptation of the TCOM expansion board. Essentially, it is the same, just shrunk to fit the CDC. The uTCOM board is a separate adapter, with its own specification document. 7.1 Overview CPM/CE Signals DIN128 The general uTCOM interface architecture is shown in Figure 7-1. uTCOM TCOM Connectors DIN128 -to60XBus Figure 7-1.
PAGE 122
uTCOM Architecture 7.2 7.2.1 • • • • • 7.2.2 Mechanical Architecture uTCOM Connector The uTCOM connector is used to connect the CDS carrier card to one of several special-purpose test/evaluation boards, most commonly the TCOM board. This card has numerous I/O, debug and communications configurations, and is connected to via two 128-pin DIN connectors.
PAGE 123
uTCOM Architecture Table 7-1. CDS uTCOM Connector Details (continued) Signal Notes MDC 5V 3.3V Ground Total Spares Bring up to next connector size Total 7.3 uTCOM Pinout For a detailed pinout, including numbering, refer to Appendix B.3, “uTCOM Connector Pinout.” The following tables detail the pinout interface between CDS uTCOM board P1 and P2 connector, to TCOM board (Table 7-2 and Table 7-3). Table 7-2.
PAGE 124
uTCOM Architecture Table 7-2.
PAGE 125
uTCOM Architecture Table 7-2. uTCOM Pin Routing to TCOM Board (P1 Connector) (continued) MPC8555E CPM (Port Name) Male uTCOM Sweezler <-> Female TCOM (Port Name) PD23 EN_T1_3 PD6 PD24 EN_T1_4 PD7 PD25 EN_T1_5 PD8 PD14 EN_T1_7 PD18 PD15 EN_T1_8 PD19 All other — NC — All other PC9 — MIIMDIO — PC9 PC10 — MIIMDC — PC10 Table 7-3.
PAGE 126
uTCOM Architecture MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 127
Appendix A Revision History This appendix provides a list of the major differences between the MPC8555E Configurable Development System Reference Manual, Revision 0 through the MPC8555E Configurable Development System Reference Manual, Revision 1. A.1 Changes From Revision 0 to Revision 1 Major changes to the MPC8555E Configurable Development System Reference Manual, from Revision 0 to Revision 1 are as follows: Section, Page Changes Book Change 33-66 MHz to 33/66 MHz.
PAGE 128
Revision History 1.3.1, 1.2 throughout this manual as Configuration 1 or Configuration 2. The configurations are: • Configuration 1 — Arcadia, Rev. 3.1 — Carrier card, Rev. 1.2 — CPU card, Rev. 1.1 — I/O card, Rev. 1.1 • Configuration 2 — Arcadia, Rev. 3.1 — Carrier card, Rev. 1.3 — CPU card, Rev. 1.1 Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3.
PAGE 129
Revision History OC3 ATM PHY OC12 ATM PHY AdTech MUX uTCOM GBit #1 Flash GBit #2 GBit #3 CPU Daughtercard BUF NVRAM Quad PHY DEBUG GBit #4 UART Local Clock H/S Clock PCI-X +2.5-V Power Figure 1-2. Carrier Block Diagram (Configuration 2) 1.3.2, 1-4 Chapter 2, 2-1 Renumber Figure 1-2 to Figure 1-3. Replace the first paragraph with the following: This chapter provides a step-by-step guide for bringing up a CDS.
PAGE 130
Revision History 2.2,2-1 Replace the first sentence in the note to read: The carrier card and processor card are packaged together. 2.2, 2-1 2.3, 2-5 Delete Step 1 and renumber the rest. Item No. 5, replace the U-boot screen dump with the following: U-Boot 1.1.3 (FSL Development) (Oct 27 2006 - 10:43:18) CPU: 8555, Version: 1.1, (0x80790011) Core: E500, Version: 2.
PAGE 131
Revision History 2.5, 2-9 In Table 2-2, replace the rows for SW 2, Bits 5 and 6 with the following: 2 5 Reserved 1 1 Reserved 6 Reserved 1 1 Reserved, see Note 2 2.5, 2-10 In Table 2-2, replace the row for SW 3, Bit 2 with the following: 3 2 DUART output select 1 0 DUART channel #2 to 2x5 (AT) header DUART channel #1 to DB9 connector 1 DUART channel #2 to DB9 connector DUART channel #1 to 2x5 (AT) header 2.5, 2-10 In Table 2-2, replace the row for SW 3, Bits 6 with the following: 3 6 2.
PAGE 132
Revision History 2.
PAGE 133
Revision History 3.1.2, 3-2 After Figure 3-2, add the following paragraph and figure: Figure 3-2 is a diagram of the CDS system for Configuration 2. OC3 ATM PHY OC12 ATM PHY AdTech MUX uTCOM GBit #1 Flash GBit #2 GBit #3 BUF NVRAM Quad PHY CPU Daughtercard DEBUG GBit #4 UART Local Clock H/S Clock +2.5-V Power PCI-X Figure 3-2. Carrier Block Diagram (Configuration 2) 3.3.
PAGE 134
Revision History 3.6, 3-12 Replace the first paragraph and note with the following: In Configuration 1, the CDS carrier card provides four 10/100 1GB-baseT Ethernet ports. Two are located on the basic carrier board and the other two on the IOCard expansion. The four ports are controlled by a Cicada CS8204 quad-PHY, which in turn receives data from three dedicated MII/GMII daughtercard connections. In Configuration 2, all four Ethernet ports on the carrier card are supported by a Marvell 88E1145.
PAGE 135
Revision History 3.6, 3-14 After Figure 3-13, add the following figure: MI RJ45 + MAG Daughtercard GMI/RGMII TSEC1 Port 0 GMII TSEC2 1 Marvell 88E1145 2 3 RGMII RGMII 10/100 RJ45 + MAG ⊗ RJ45 + MAG RJ45 + MAG 125 MHz Figure 3-12. CDS Ethernet Architecture (Configuration 2) 3.6, 3-14 In Table 3-17 change the fifth column heading to read: ‘CS8204 PHY or Marvell 88E1145’. Remove the references to note 3 in the table and note 3 at the end of the table.
PAGE 136
Revision History 3.8, 3-19 3.8, 3-19 Table 3-21, remove the HS_CLK row and note 1 at the end of the table. Replace Figure 3-15 with the following: PCICLK PCI SLOT CDC 16 MHz OSC I2C/ Switch ICS525-02 PCICLK MUX SYSCLK RTC_CLK LBCLK 125 MHz GTX_CLK OSC Local Bus 3.8, 3-21 3.8.1, 3-21 3.13, 3-27 In the last paragraph, delete the first sentence. Delete Section 3.8.1.
PAGE 137
Revision History 5.5.4, 5-12 Slot #2 Slot #3 Slot #4 Slot #5 In Table 5-7, for Slots #2, #3, #4, and #5, the Slot 5 information has changed in the ‘Attached Devices by Connection’ column.
PAGE 138
Revision History Appendix C CDS Carrier BOM, Rev. 1.2 Appendix D, D-1 This appendix provides CDS Carrier BOM for Rev. 1.2. Replace title and paragraph as follows: Appendix D CDS Carrier Schematics, Rev. 1.2 Appendix E, E-1 This appendix provides CDS Carrier board schematics for Rev. 1.2. Add new appendices E and F (renumber remaining appendices): Appendix E CDS Carrier BOM, Rev. 1.3 This appendix provides CDS Carrier BOM for Rev. 1.3. Appendix F CDS Carrier Schematics, Rev. 1.
PAGE 139
Appendix B Pinouts B.1 Carrier/DaughterCard Connectors Pinout Table B-1. Daughtercard Connector (Left) Definition and Pinout Pin A 1 GND 2 U1_TP B VCC_2.5 C D E F G H J K U1_SI GND PA0 PA1 GND PA2 PA3 VCC_2.5 U1_SO U2_SI GND PA4 PA5 GND PA6 PA7 3 U1_TN U1_OC GND U2_SO PA8 GND PA9 PA10 VCC_2.5 PA11 4 VCC_2.5 U2_OC U1_RTS GND PA12 PA13 GND PA14 PA15 GND 5 U2_TP GND U1_CTS U2_RTS GND PA16 PA17 VCC_2.5 PA18 PA19 6 U2_TN VCC_2.
PAGE 140
Pinouts Table B-1. Daughtercard Connector (Left) Definition and Pinout (continued) Pin A 31 GND 32 GNT# 33 C D E F G H J K AD31 GND PAR AD35 GND AD49 AD56 VCC_3.3 VCC_3.3 AD30 C_BE0 GND C_BE3 AD39 GND AD11 AD5 REQ# GNT64# GND C_BE1 C_BE2 GND AD40 C_BE6 VCC_3.3 AD4 34 VCC_3.3 REQ64# AD29 GND AD20 IDSEL GND C_BE4 AD10 GND 35 M66EN GND AD28 AD24 GND DEVSEL AD41 VCC_3.3 AD9 AD3 36 PCIXCAP SERR# VCC_3.
PAGE 141
Pinouts Table B-2. Daughtercard Connector (Right) Definition and Pinout (continued) Pin A B C D E F G H J K 26 PCIRST# VCC_3.3 DMACK0 LB_GP3 GND LB_A3 LB_A9 GND LB_A21 LB_A27 27 CFGRST DMADN1 GND LB_GP4 LB_CS3 GND LB_A10 LB_A16 VCC_3.3 LB_A28 28 VCC_3.3 DMADN0 DMARQ1 GND LB_CS2 LB_A4 GND LB_A17 LB_A22 GND LB_GP5 29 MCP GND DMARQ0 30 INT13 INT14 VCC_3.3 31 GND INT11 INT15 32 INT10 VCC_3.3 33 INT7 34 VCC_3.3 35 GND LB_A5 LB_A11 VCC_3.
PAGE 142
Pinouts Table B-3.
PAGE 143
Pinouts Table B-3. Daughtercard High-Speed Connector Definition and Pinout (continued) A B C 63 GND GND GND 64 HS_X2p GND HS_X1p 65 HS_X2n GND HS_X1n 66 GND GND GND 67 HS_X4p GND HS_X3p 68 HS_X4n GND HS_X3n 69 GND GND GND 70 GND 71 GND 72 GND 73 GND GND GND 77 GND GND GND 79 GND 80 GND 81 GND GND 82 GND 83 GND 84 GND 85 GND GND GND GND GND GND 86 B.
PAGE 144
Pinouts Table B-4. IOCard Connector Definition and Pinout (continued) Pin A B C D E 7 GND EVENT1 VCC_3.3 T3_LED4A 8 GND EVENT2 VCC_3.3 T3_LED4C 9 GND GND GND VCC_3.3 GND 10 T4_TXIP_A GND T4_TXIP_B VCC_3.3 T4_LED1A 11 T4_TXIN_A GND T4_TXIN_B VCC_5 T4_LED1C 12 GND GND GND VCC_5 T4_LED2A 13 T4_TXIN_C GND T4_TXIP_D VCC_5 T4_LED2C 14 T4_TXIN_C GND T4_TXIN_D VCC_5 T4_LED3A 15 GND GND GND VCC_5 T4_LED3C VCC_5 T4_LED4A 16 GND 17 B.
PAGE 145
Pinouts Table B-5. uTCOM Connector (Right) Definition and Pinout (continued) Pin A B C D E F G H J K 21 GND PA29 PB13 VCC_3.3 PC13 PC29 GND PD29 CX13 VCC_5 22 PA14 PA30 VCC_3.3 PB30 PC14 GND PD14 PD30 VCC_5 CX30 23 PA15 VCC_3.3 PB14 PB31 GND PC30 PD15 VCC_5 CX14 CX31 24 VCC_3.3 PA31 PB15 GND PC15 PC31 VCC_5 PD31 CX15 GND 25 SDA 26 SCK 27 GND 28 MDIO 29 MDC 30 VCC_3.3 31 LB_GP0 32 LB_GP1 33 GND INT7 VCC_3.3 34 LB_GP2 VCC_3.
PAGE 146
Pinouts MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 147
Appendix C CDS Carrier BOM, Rev. 1.2 This appendix provides CDS Carrier BOM for Rev. 1.2. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 148
Board Station BOM file Date : NOV 1 2005 Variant : CDS_Carrier rev 1.2 Line item 68, J12, is now a NO POP component ITEM_NOCOMPANY PART NO. 1 2 3 4 5 6 1-1605458-1 103167-2 103309-1 105-1089-00 1210YG106ZAT2A 7 8 9 10 11 12 13 GEOMETRY pcb_carrier conn_rj45_mag_led header_ra_2x5 header_2x5_shrouded BOM CDS Carrier rev 1.2a updated 12_MAY_05 BOM CDS Carrier rev 1.2B updated 1_SEP_05 BOM CDS Carrier rev 1.2C updated 1_NOV_05 COUNT DESCRIPTION cc1210 1 2 1 1 3 9 conn.rj45_cat5_mag_led.
PAGE 149
20 21 22 23 24 25 26 27 28 APA150-FG256 AT24C64AN-10SI-2.7 CY7B9950AC DEM9PL DS1553WP-120 DS1834S DS9034PCX E13W1F2C-77.760M EEFUE0G221R fbga256 so8 tqfp32 conn_db9_plg_ra pcm34 so8 osc_smd_e13j1 cc_7.3x4.3_ue 1 1 1 1 1 2 1 1 19 apa150.1of2.fbga256, ACTEL at24c64a.s08, ATMEL cy7b9950ac.tqfp32, CYPRESS conn.db9.plug.rta, ITT Cannon ds1553wp_120.pcm34, DallasSemi ds1834s.so8, DALLAS SEMI. POWERCAP osc.3_3v.diff.smd, 77.
PAGE 150
48 49 50 51 MAX4372FEUK-T MBRS140T3 MCCA101K0NRT MCCA104K0NRT sot23_5p smb_403a cc0402 cc0402 1 1 1 240 max4372f.sot23_5, Maxim mbrs140t3.smb, MOT cap, 100pF, SMEC cap, 0.
PAGE 151
C188 C189 C190 C191 C194 C195 C197 C199 C200 C201 C202 C203 C204 C205 C206 C207 C209 C210 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 C233 C236 C237 C238 C239 C240 C241 C242 C243 C244 C245 C246 C248 C249 C250 C251 C252 C253 C256 C258 C259 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 C275 C276 C277 C279 C280 C281 C283 C284 C287 C288 C294 C295 C296 C299 C301 C303 C309 C311 C312 C313 C314 C315 C316 C317 C318 C319 C320 C321 C3
PAGE 152
52 53 MCCA470K0NRT MCCE102KONRT cc0402 cc0402 3 34 cap, 47pF, SMEC cap, 1000pF, SMEC 54 55 56 57 58 59 MCCE103KONRT MCR10-EZHM-J-5R0 MMSZ6V2T1 MPC9259FA MPC962308DT-1H NOT_A_COMPONENT cc0402 rc0805 sod_123 lqfp32 tssop16 tp_pth 1 1 1 1 2 31 cap, 0.01uF, SMEC res, 5, Rohm MMSZ6V2T1.sod123, Motorola mpc9259fa.lqfp32, MOTOROLA mpc962308, Freescale test.pth, None 60 61 62 63 64 65 Not_a_component P6880 PCA9557PW PM5357-B1 PM5384NI QSE-020-01-L-D-A jump_2x1_1mil conn_banjo tssop16 sbga304_1.
PAGE 153
67 68 RC5051M RC73L2Z000JT sol20 rc0402 1 29 rc5051m.
PAGE 154
81 82 RK73H1ETTP1500F RK73H1ETTP1580F rc0402 rc0402 3 4 res, 150, KOA res, 158, KOA 83 84 85 86 RK73H1ETTP15R0F RK73H1ETTP2001F RK73H1ETTP2R70F RK73H1ETTP3010F rc0402 rc0402 rc0402 rc0402 3 1 2 5 res, 15, KOA res, 2.00K, KOA res, 2.7, KOA res, 301, KOA 87 RK73H1ETTP47R5F rc0402 35 res, 47.
PAGE 155
97 98 99 100 101 102 103 T510X477M006AS TPSE227K010R0100 VSC8204VX WSL2512R010F YFS-20-03-H-05-SB-K pcix_econ_64b_3.3v screw QTH-090-02-F-D-A RC73L2Z000JT RC73L2Z330JT cct_casee cct_casee pbga388_35x35 rc2512 header_array_5x20 econ_pcix64b_3.3v_Signal8_ NO POP Components qth_2x90_gnd rc0402 rc0402 1 3 1 1 1 1 2 cap_tant, 470uF, Kemet cap_tant, 220uF, AVX cis8204.ports.1of3.pbga388, CICADA res, 0.010, DALE header.5x20.1of3, Samtec pcix_edgeconn_64bit, MOT screw 0 0 0 conn.qsh.2x90.
PAGE 156
CDS Carrier BOM, Rev. 1.2 MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 157
Appendix D CDS Carrier Schematics, Rev. 1.2 This appendix provides CDS carrier board schematics for Rev. 1.2. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 158
1 2 4 3 5 6 7 8 A A B B Carrier C C D D Freescale Semiconductor freescale TM semiconductor 1 7700 W. Parmer Ln Austin, Texas 78729 2 Project: CDS_Carrier Date Changed: 11/8/2005 Engineer: Revision: Title: Cover Story Gary Milliorn Page: 01 Time Changed: 10:25:20 am 1.
PAGE 159
1 2 3 4 5 6 1. Unless otherwise specified: All resistors are SMD0402, in ohms, 0.08W, +/-5% All capacitors are SMD0402, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. A 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: 3.
PAGE 160
1 2 3 4 5 6 7 8 A A Configuration Logic uTCOM Connector 05 ATM PHYs 26-27 29-32 System Logic 06-07 10/100/1000baseT Connectors 21 Power Supplies B CPM Select LocalBus Debug 24-25 34 B 08 Local Bus Flash + NVRAM Quad Ethernet PHY Clocks 19-20 33-34 09-10 Mezzanine Connectors I2C Devices High-Speed Connector IOCard Connector 11 22 15-16 12-14 Test Access C C PCI/PCI-X Connector 11, 34 HmZd Interface 18 17 D D freescale TM semiconductor 1 Freescale Semiconductor
PAGE 161
1 2 3 5 4 6 7 8 335mm [13.25] A A LEDs Opto FCI Opto QS QS QS QS QPHY AdTech RJ45 QS QS MISC POWER ATM ATM PHY 1 PHY 2 RJ45 130mm CPLD FCI FCI UART B Samtec [5.2] FLASH PromJet FLASH CLK SWITCH B Mictor SWITCH P6880 Mictor P6880 SWITCH HMZD SWITCH KEY KEY POWER NVRAM Mictor C C .062 D Freescale Semiconductor freescale TM semiconductor 1 7700 W.
PAGE 162
1 2 3 4 5 7 6 8 VCC_3.3 SCL IO0 SDA IO1 2 1K 1K 16 15 14 13 12 11 10 9 1_ON 2_ON 3_ON 4_ON 5_ON 6_ON 7_ON 8_ON 2C 3C 4C 5C 6C 7C 8C 2 3 4 5 6 7 8 8_ON 8C 8 SW3 10 7_ON 7C 7 1C 11 9 6_ON 6C 1 12 5_ON 5C sw.8spst.cts 13 4_ON 4C 8 6 7 5 6 4 5 15 4 14 3 16 2 3_ON 1 2_ON 8 1_ON 7 3C 6 3 5 2C 4 SW2 1 RN5 RN6 7B8,11A8,26C1 3 1C pca9557pw.tssop16 SCL SDA 2 2 VCC_3.3 7B8,11A8,26C1 1 1 A 9 10 9 A sw.8spst.
PAGE 163
1 2 3 5 4 VCC_3.3 6 7 8 VCC_2.5 U24 apa150.1of2.fbga256 E6 F7 VDDP_1 VDD_1 VDDP_2 VDD_2 VDDP_3 VDD_3 VDDP_4 VDD_4 VDDP_5 VDD_5 F8 E7 C237 0.1uF C229 0.1uF C178 0.1uF C157 0.1uF C179 0.1uF C156 0.1uF F9 E10 C199 0.1uF C209 0.1uF E11 A K5 J9 conn.
PAGE 164
1 2 4 3 5 6 7 8 LB_A(0:31) 6B1,14C8,15D8,27D1 VCC_3.3 10K 10K R124 U24 R129 LB_GPL(0:5) 6C1,14A8,26C1,34C1 apa150.2of2.
PAGE 165
1 2 3 4 5 6 7 8 VCC_5 L2 AREA_FILL AREA_FILL FILT_VCC 1.1uH + C145 0.1uF C136 220uF 10V + + C62 220uF 10V C192 220uF 10V + C91 220uF 10V + + C135 220uF 10V + C193 220uF 10V C146 220uF 10V C128 1.0uF C129 1.0uF C134 1.0uF C147 0.1uF A A CR2 VCC_12 MMSZ6V2T1 VCC_5 sod_123 R91 POWER_TRACE POWER_TRACE THERMAL HEATSINK PLANE FILL 10 cm^2 on top layer VCCQP 47 6 7 R75 13 1 C90 1.0uF VCCA VCCP C55 1.
PAGE 166
1 2 4 3 7 6 5 R164 UT_CDCPCICLK 33 8 CDC_PCICLK 13B8 1CM_MAX R198 UT_CDCSYSCLK 33 CDC_SYSCLK 12C1 1CM_MAX A A PCICLK_COPY VCC_3.
PAGE 167
1 2 3 4 5 6 7 8 SYNCHRO* 5D8 U29 mpc9259fa.lqfp32 8 HIGH-SPEED EXTERNAL CLOCK XTAL_IN NC Optional high-speed/flexible clock source. 9 A XTAL_OUT NC 31 DP_HSCLK HSCLK 30 DP_HSCLK HSCLK HS_TXCLKp HS_TXCLKn FOUT FOUTn 7 16D1 A 16D1 FREF_EXT 20 XTAL_SEL NC1 CFGRST* HSCLK_LD* 5B1,7A1,14C1,26D1 6D1 11 3 NC2 NC3 TEST HSCLK_DATA HSCLK_CLK 6B1 6C1 VCC_3.3 16 NC 21 P_LOAD S_LOAD NC 24 NC SYNC_CLK 26 74lvc1g125.sc70 2 1 SDATA VCC_3.
PAGE 168
1 3 2 VCC_3.3 4 6 7 8 VCC_3.3 VCC_3.3 VCC_3.3 5 8 A A VCC U2 ltc4300_1.ms8 CDC_SCL 14D1 3 CDC_SDA 14C1 SCL_I SCL_O SDA_I SDA_O 6 R48 R47 4.7K 4.7K 2 SCL 7 SDA 5A1,7B8,26C1 5A1,7B8,26C1 5 1 READY ENABLE NC GND 4 U1 VCC_2.5 at24c64a.s08 R37 100 D10 5 DATA CARRIER CONFIG Addr=0x56 6 CLK Green OVdd A0 A2 R36 100 D9 1 3 2 WC A1 7 NC B B Green Vdd3 VCC_3.3 R28 220 VCC_3.3 REMOTE CONTROL ACCESS HEADER D1 0 VCC_3.
PAGE 169
1 2 13A1,25A1,26A1 4 5 6 7 8 CPM_CLASS CPM_CLASS UART1(0:3) UART2(0:3) 23A1 23C1 TSEC1(0:24) TSEC2(0:24) TSEC3(0:24) 19A1 19D1 19A8 A 3 PA(0:31) PB(4:31) 13A1,24A1,26A1 A USB1(0:2) USB2(0:2) 22C1 22C1 VCC_2.5 VCC_2.5 VCC_2.5 J10 conn.megarray.10x40.2of5 J10 conn.megarray.10x40.1of5 FCI 74390-001 A1 B1 0 A2 B2 1 A3 B3 A4 B4 A5 B5 FCI J10 conn.megarray.10x40.
PAGE 170
1 2 3 4 PA(0:31) PB(4:31) 12A1,24A1,26A1 12A1,25A1,26A1 5 6 7 8 CPM_CLASS CPM_CLASS MDIO MDC A A 20A1,26C1 20A1,26C1 J10 J10 conn.megarray.10x40.5of5 conn.megarray.10x40.
PAGE 171
1 2 4 3 5 6 7 8 PC(0:31) PD(4:31) CX(0:31) 15A1,24A1,25A1,26A1 15A1,24A1,25A1,27A1 15A1,27A1 A A LB_LBCTL LB_GPL(0:5) J11 conn.megarray.10x40.2of5 J11 conn.megarray.10x40.1of5 FCI 74390-001 VCC_2.5 FCI A1 B1 4 A2 B2 9 A3 B3 10 14 0 VCC_2.5 A4 B4 18 A5 B5 22 A6 B6 23 A7 B7 27 A8 B8 A9 B9 31 VCC_2.
PAGE 172
1 2 3 5 4 6 7 8 PC(0:31) PD(4:31) CX(0:31) 14A1,24A1,25A1,26A1 14A1,24A1,25A1,27A1 14A1,27A1 A A J11 J11 VCC_2.5 VCC_2.5 conn.megarray.10x40.4of5 FCI 8 H1 G2 H2 FCI 0 G3 H3 5 G4 H4 7 21 G5 H5 26 G6 H6 11 G7 H7 13 G8 H8 13 4 H9 17 G10 H10 19 18 G11 H11 23 G12 H12 23 G13 H13 25 G14 H14 G15 G16 9 G9 B VCC_2.5 conn.megarray.10x40.
PAGE 173
1 2 4 3 5 6 7 8 A A J12 J12 J12 conn.qsh.2x90.1of3 conn.qsh.2x90.2of3 conn.qsh.2x90.
PAGE 174
1 2 3 4 5 6 7 8 HS_TD(0:39) 16D1 HS_RD(0:39) 16C1 P4 conn.banjo 19 A A15 P7 CLK_QUAL18 RFRM A A13 CLK_QUAL+ 17 B12 16 B10 15 A12 conn.amp.HMZd.40pr.recpt.
PAGE 175
1 2 3 4 5 6 7 8 Place sense Rs within 1cm of edge connector SENSE_IRDY* SENSE_TRDY* SENSE_STOP* 7C8 7A1 7C8 A PCICLK PCIRST* 9B1 R201 10 PCI_EDGE R202 10 PCI_EDGE R203 10 PCI_EDGE P8 pcix_edgeconn_64bit B16 B9 CLK PCI B11 RST PCI_FRAME* PCI_DEVSEL* PCI_IRDY* PCI_TRDY* PCI_STOP* 12C8 12C8 12C8 12C8 12D1 PCI A34 PCI B37 PCI B35 PCI A36 PCI A PRSNT1 A15 7B8,14C1 PRSNT2 NC A4 FRAME TDI DEVSEL TDO IRDY TCK TRDY TMS STOP TRST B4 NON-STANDARD B2 Allow PCI/HI
PAGE 176
1 2 4 3 5 6 7 8 A A U6 cis8204.macs.2of3.
PAGE 177
2 1 3 4 VCC_3.3 VCC_3.3 5 6 7 8 VCC_3.3 R65 U6 2K VCC_L cis8204.sys_pwr.3of3.pbga388 MDC MDIO IRQ*(11:0) 13A8,26C1 A 13A8,26C1 R1 VREFP P2 G25 MDIO R2 5 6B8,7A1,14D1,18A8,26D1,28C1,29C8,31C8,34B8 EPHY_ADR(4:2) 6B1 H23 MDC 4 N1 3 N2 2 P1 1CM_MAX A REF_FILT R50 47.5 MDINT PHYADDR4 REF_REXT PHYADDR3 VREFN G26 C35 1.0uF C34 1.
PAGE 178
1 2 3 4 5 6 7 R54 16 8 D12 Red 180 R60 Gb_0 D14 Red 14 180 A 10b_0 A U6 cis8204.ports.1of3.pbga388 TP11 TP10 TP8 K1 $V K2 $V L1 $V J6 MODE1_2 MODE1_0 G1 G2 MODE0_2 MODE0_0 H2 DUPLEX_2 DUPLEX_0 $V $V $V conn.rj45_cat5_mag_led.ra TP2 13 TP1 TP5 D1 L1A D2 L1K 100baseT 1 TP13 TP9 TP12 T3_TXIP_A B14 R14 R13 47.5 47.5 1% 1CM_MAX 1% 1CM_MAX T3_TXIN_A T3_TXIP_B 22B1 22A1 R12 47.5 1% 1CM_MAX A12 R11 47.5 1% 1CM_MAX A11 22A1 47.5 1% 1CM_MAX A10 R9 47.
PAGE 179
2 1 21D1 3 5 4 6 7 8 ENET_LEDS(1:16) A A 21B1 T3_TXIP_B T3_TXIN_B DIFF_PHY DP-3B DIFF_PHY DP-3B T3_TXIP_D T3_TXIN_D DIFF_PHY DP-3D DIFF_PHY DP-3D 21B1 21B1 21B1 J7 header.5x20.
PAGE 180
2 1 3 4 5 6 VCC_5 VCC_5 7 8 VCC_3.3 U47 lt1331cg.ssop28 A SOUT0 25 23 U41 idtqs3vh257.tssop16 UART1(0:3) 1 2 12A1 1 3 YA A0 RTS0 19 4 16 NC 24 5 2 6 B0 YB SIN0 7 22 21 B1 NC CTS0 0 11 0 10 3 14 3 5B8 13 UART_SEL 1 $V 15 A D1OUT D2IN D2OUT D3IN D3OUT 5 SHORT_SERIAL 7 SHORT_SERIAL 11 SHORT_SERIAL J15 conn.db9.plug.rta 1 2 3 4 5 DRVDIS A1 NC 2 D1IN YC C0 20 18 9 NC 13 C1 YD D0 VCC_3.3 C328 0.1uF SEL VCC EN GND C329 0.1uF 26 C315 0.
PAGE 181
1 2 3 4 5 6 7 8 PA(0:31) 12A1,13A1,26A1 PC(0:31) PD(4:31) 14A1,15A1,25A1,26A1 14A1,15A1,25A1,27A1 18 A U18 idtqs3vh16233pa.tssop56 1 19 54 20 4 21 51 22 7 23 48 24 25 10 45 28 15 25 40 22 18 6 37 5 21 10 34 9 24 8 31 A1 1B1 A2 1B2 A3 1B3 A4 1B4 A5 1B5 A6 1B6 A7 1B7 A8 1B8 A9 1B9 A10 1B10 A11 1B11 A12 1B12 A13 1B13 A14 1B14 A15 1B15 A16 1B16 2B1 2B2 2B3 VCC_3.3 2B4 2B5 14 B C131 0.1uF 43 C155 0.
PAGE 182
1 3 2 4 6 5 7 PB(4:31) PC(0:31) PD(4:31) 14A1,15A1,24A1,27A1 9 E3 A U17 idtqs3vh16233pa.tssop56 1 11 54 17 4 21 51 4 48 25 7 30 10 30 45 22 15 23 40 24 18 25 37 31 21 22 34 26 24 27 31 A1 1B1 A2 1B2 A3 1B3 A4 1B4 A5 1B5 A6 1B6 A7 1B7 A8 1B8 1B9 A9 A10 1B10 A11 1B11 A12 1B12 A13 1B13 A14 1B14 A15 1B15 A16 1B16 2B1 2B2 2B3 VCC_3.3 2B4 2B5 14 B 43 C45 0.1uF C66 0.1uF ATM2_TXDATA(7:0) ATM2_RXDATA(7:0) U7 idtqs3vh16233pa.
PAGE 183
1 4 5 6 7 8 XPA(10:31) XPB(4:27,29:31) XPC(1,4,6:17,19,21:22) 24D8 25C8 24D8,25C8 PA(0:31) PB(4:31) PC(0:31) 12A1,13A1,24A1 12A1,13A1,25A1 A 3 2 14A1,15A1,24A1,25A1 A VCC_5 VCC_3.3 VCC_3.3 VCC_3.3 J3 conn.megarray.10x40.1of5 FCI 74390-001 0 A1 B1 1 A2 B2 A3 B3 VCC_3.3 VCC_3.3 J3 J3 conn.megarray.10x40.2of5 FCI 16 conn.megarray.10x40.
PAGE 184
2 1 3 4 5 6 7 8 PD(4:31) 14A1,15A1,24A1,25A1 XPD(5:6,14:17,20:28,30:31) 24D8,25C8 A A CX(0:31) 14A1,15A1 VCC_5 VCC_5 VCC_5 VCC_5 J3 J3 conn.megarray.10x40.4of5 FCI conn.megarray.10x40.
PAGE 185
2 1 3 4 5 6 ADTECH RX 7 8 ADTECH TX A A ATM1_TXSOC 24C8,29B1 ATM1_TXDATA(15:0) ATM1_TXPRTY 24A8,29A1 24C8,29B1 ATM1_TXADD(2:0) ATM1_RXADD(2:0) ATM1_RXDATA(15:0) 24C8 24C8 24A8,29C1 Place and Group Connectors per spec ATM1_RXSOC 24C8,29C1 J4 QSE-020-01-L-D-A J5 QSE-020-01-L-D-A B 0 1 2 1 0 2 1 2 3 4 3 2 3 4 3 5 5 6 4 5 5 6 4 7 7 8 6 7 7 8 8 9 10 9 8 9 10 9 10 11 12 11 10 11 12 11 13 13 14 12 13 13 14 12 15 15 16 14 15 15 16 1
PAGE 186
1 3 2 4 5 6 7 8 VCC_3.3 VCC_3.3 FB4 AREA_FILL R78 R79 220 330 AREA_FILL HI1206N101R-00 SHORT_POWER C113 0.1uF U9 5 12 VDD1 VDD2 FBK 6 7 24C8,28D1 24C8,28A1 K20 J23 4 J22 5 J21 6 H22 7 H21 0 IN 21424900 11369040 8 16 NC G23 10 G22 11 G21 12 G20 13 F22 14 F21 15 E23 TDAT1 SD TDAT3 RXDp TDAT4 RXDn TDAT5 TDREF0 TDAT6 TDREF1 TDAT7 APS0 TDAT8 APS1 TDAT9 APS2 TDAT10 APS3 TDAT11 APS4 TDAT12 RALRM TDAT13 RCLK TDAT14 RFPO TDAT15 TCLK R106 0.
PAGE 187
2 1 3 4 5 6 7 8 VCC_3.3 R144 100 C242 0.1uF R145 15 A VCC_3.3 U23 C255 10uF VCC_3.3 PM5357-B1 1% A U23 C256 0.1uF PM5357-B1 pm5357.vdd.2of3.sbga304 pm5357.vss.3of3.sbga304 R117 A1 W20 VDD0 E20 VDD1 C182 0.1uF C183 0.1uF C184 0.1uF C186 0.1uF C185 0.1uF C187 0.1uF VDD2 AA21 W2 VDD3 PBIAS0 VDD4 PBIAS1 VDD5 PBIAS2 AB2 AB22 AC1 B2 C241 0.1uF C240 0.1uF C223 0.1uF C202 0.1uF C224 0.1uF C215 0.1uF B22 A16 R3 A18 A22 PBIAS3 QAVD0 VDD9 QAVD1 E3 AA2 C225 0.
PAGE 188
1 2 3 4 5 6 7 8 VCC_3.3 VCC_3.3 FB6 AREA_FILL R80 R81 220 330 AREA_FILL SHORT_POWER C71 0.
PAGE 189
1 2 3 5 4 6 7 8 A A U25 PM5384NI pm5384.pwr.2of2.stpbga196 VCC_3.3 VCC_3.3 C1 VDDO0 R138 2.7 1% K5 SHORT_POWER C257 10uF C4 AVD0 VDDO1 AVD1 VDDO2 C6 H5 PWR C10 C244 0.1uF C258 0.1uF C232 0.1uF C245 0.1uF C206 0.1uF C190 0.1uF C265 0.1uF C259 0.1uF C262 0.1uF C191 0.1uF C207 0.1uF C233 0.1uF C246 0.1uF C260 0.1uF C261 0.1uF C263 0.1uF C264 0.1uF C189 0.1uF C204 0.
PAGE 190
1 2 3 4 5 6 7 8 A A CLA(23:0) 6B1,7B1,28B1,29D8,31D8,34B1 FLASH0_CS* FLASH1_CS* PJET_CS* LB_RD* LB_WR* 6C8 6C1 7A8 B 7B8,28C1,29C8,31C8,34B1 7C8,28D1,29C8,31C8,34B1 B MEM_RST* 7C8 VCC_3.3 25 1 24 am29lv641d.
PAGE 191
1 2 3 4 6 5 7 8 VCC_3.3 U51 DS1553WP-120 12 30 11 29 10 28 5 pcm34 VCC A12 VCC_3.3 A11 A10 9 27 17 GND A9 A 8 26 7 25 6 24 5 23 4 22 3 21 2 20 A A8 0 18 NVRAM_CS* LB_RD* LB_WR* 7B8,28C1,29C8,31C8,33B1 4.7K 4.7K 4.7K 10 R152 11 R184 4.7K 4.7K 4.7K R183 R151 R136 R190 9 8 7 6 R189 4.7K IRQ*(11:0) NVWD_RST* 4.7K 11 4.7K 1 4.7K LB_D(0:31) 4.7K 7 4.
PAGE 192
1 3 2 4 5 6 7 8 A A B B C C D D freescale TM semiconductor 1 Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 2 Project: CDS_Carrier Date Changed: 11/8/2005 Engineer: Revision: Title: --reserved-- Gary Milliorn Page: Time Changed: 10:29:23 am 1.
PAGE 193
1 2 A 3 4 5 6 7 8 A VCC_3.3 C330 C337 C266 C340 C47 C331 C334 C333 C341 C325 C336 C174 C320 C173 C172 C171 C170 C176 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C339 C335 C324 C169 C92 C194 C345 C343 C319 C342 C326 C338 C177 C51 C195 C42 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.
PAGE 194
CDS Carrier Schematics, Rev. 1.2 MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 195
Appendix E CDS Carrier BOM, Rev. 1.3 This appendix provides CDS Carrier BOM for Rev. 1.3. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 196
Item Number: 750-21600 Description: SUB ASSEMBLY, SCHEMATIC PARTS,700-21600. CARRIER 1.3 C ECO13129 Item Revision: Item 1 2 Description SUB ASSEMBLY, SCHEMATIC PARTS,700-21600. CARRIER 1.3 CAP CER 0.01UF 50V 10% X7R 0402 Qty Ref Des 38 C286,C360-C396 3 CAP TANT ESR=0.
PAGE 197
14 CAP TANT LOW ESR 22UF 6.3V 10% 0805 7 15 CAP TANT LOW ESR 68UF 25V CASE D 2 C83,C196,C347-C351 C352,C422 16 IND FER BEAD 330OHM@100MHZ 2.5A 25% 8 FB8-FB15 17 IND FER BEAD 100 OHM@100MHZ 3A -- 1206 4 FB4-FB7 18 IND PWR CHK 1.06UH@100KHZ 16A 20% 0505 1 L2 19 CON 8X10 RA SHLD SKT TH 2.5MM SP AU 1 P7 20 CON 3 PWR PLUG RA SHRD TH -- AU 2 P5,P6 21 CON 1X2 GIG MAG-JACK TAB-UP WITH LEDS 2 J18,J19 22 HDR 2X5 TH 100 MIL CTR .
PAGE 198
55 1 56 IC XCVR QUAD GIG E HSLBGA364 ROHS COMPLIANT IC LIN AMP HIGH SIDE CURRENT SENSING SOT-23 U65 1 U14 57 IC LIN NON ISOLATED DC/DC CONVERTER DIP 12 1 U80 58 IC ATM-SONET PHY -- 3.3V SBGA 304 1 U23 59 IC FPGA 150K GATE 3.3V BGA-256 1 U24 60 IC,EEPROM,NOR FLASH,4MX16,CMOS,TSSOP,48PIN,PLASTIC, ROHS COMPLIANT 2 U49,U54 61 IC MEM EEPROM 8192X8 400KHZ 2.7-5.5V SOIC 8 1 U1 62 LED GRN SGL 2.2V 20MA 0603 2 D9,D10 63 LED RED SGL 1.8V 25MA 0603 20 D1-D8,D11-D22 64 RES MF 22.
PAGE 199
89 RES MF 2.7K 1/16W 5% 0402 2 R211,R212 90 RES MF 10.0 OHM 1/16W 1% 0402 3 R201-R203 91 RES MF 1.0K 1/16W 5% 0402 7 R25,R45,R46,R90,R117,R299,R385 92 RES MF 5.11K 1/16W 1% 0402 4 R290-R293 93 RES MF 511 OHM 1/16W 1% 0402 1 R215 94 RES MF 5.0 OHM 1/8W 5% 0805 1 R176 95 RES MF 4.
PAGE 200
CDS Carrier BOM, Rev. 1.3 MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 201
Appendix F CDS Carrier Schematics, Rev. 1.3 This appendix provides CDS carrier board schematics for Rev. 1.3. Table F-1 lists the hardware differences between carrier card Rev. 1.2 and Rev. 1.3. Table F-1. Differences Between Carrier Card Rev. 1.2 and Rev. 1.3 Item No. What is Changed on CDS Carrier Card Rev. 1.3 Schematic Sheet No. 1 Replace Cicada Quad PHY with MARVELL Quad PHY. Also added level shifters. All four Ethernet ports are connected with the PHY.
PAGE 202
Carrier freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 203
Page 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Schematic Notes 1. Unless otherwise specified: All resistors are SMD0402, in ohms, 0.08W, +/-5% All capacitors are SMD0402, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 2.
PAGE 204
Configuration Logic uTCOM Connector 05 ATM PHYs 26-27 29-32 System Logic 06-07 10/100/1000baseT Connectors 19 Power Supplies LocalBus Debug CPM Select 24-25 34 08 Quad Ethernet PHY Clocks Local Bus Flash + NVRAM 19-22 09-10 33-34 Mezzanine Connectors I2C Devices High-Speed Connector 11 12-14 15-16 Test Access HmZd Interface PCI/PCI-X Connector 11, 34 18 freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 205
.062 freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 LAYER 6 LAYER 7 LAYER 8 LAYER 9 LAYER 10 LAYER 11 LAYER 12 LAYER 13 LAYER 14 LAYER 15 LAYER 16 LAYER 17 LAYER 18 Project: Revision: COMP SIGNAL SIGNAL PLANE SIGNAL SIGNAL PLANE PLANE SIGNAL SIGNAL PLANE SIGNAL SIGNAL PLANE SIGNAL SIGNAL SOLDER 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.
PAGE 206
REMOTE CONTROL 1+2 ADDR=0x18+0x19 REMOTE CONTROL 3+4 ADDR=0x1A+0x1B freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 207
ACTEL PROGRAMMING HEADER Locate within 3" of device. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 208
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDC_Carrier 1.
PAGE 209
THERMAL HEATSINK PLANE FILL 10 cm^2 on top layer POWER SUPPLY LAYOUT RULES 1. All components in the power path (large/red bus) should be on the same layer, with area filled connections. 2. No vias or thermal reliefs allowed on power path components. 3. Ground plane connections should be made with two vias close to the component. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 210
SPECIAL PLACEMENT PLACE BOTH ICS580 NEXT TO EACH OTHER LOCAL RESET Non-re-config reset. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 211
HIGH-SPEED EXTERNAL CLOCK Optional high-speed/flexible clock source. DEFAULT=124MHz LOCAL SYSTEM CLOCK Used on non-PCI HIP boards or stand-alone. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 212
CARRIER CONFIG Addr=0x56 REMOTE CONTROL ACCESS HEADER POWER-ON RESET Re-config reset. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 213
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 1/27/2006 CDS_Carrier 1.
PAGE 214
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 215
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 216
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 217
Expansion Ports freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 218
The high-speed protocol signals are routed THROUGH the Tek P6880 connectors, despite appearances! Yes, the connector connections are connected correctly! Polarity differences are handled in the disassembler. Receive Path To processor from motherboard/target. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 219
Place sense Rs within 1cm of edge connector NON-STANDARD Allow PCI/HIP card to reset motherboard (motherboard-dependant option also). freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 220
ETHERNET PORT #1 ETHERNET PORT #2 freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 221
+2.5V +1.0V freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 222
ETHERNET PORT #3 ETHERNET PORT #4 freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 223
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 224
SERIAL PORT #1 Primary Serial Port SERIAL PORT #2 Secondary Serial Port freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 225
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 226
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 227
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 228
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 229
ADTECH RX ADTECH TX Place and Group Connectors per spec freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 230
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 231
SENSITIVE POWER FILTERS’ Capacitors without VCC_3.3V resistors MUST be placed near corresponding power pad. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 232
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 233
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 234
FLASH BANK 2 FLASH BANK 1 freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDC_Carrier 1.
PAGE 235
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: Date Changed: 2/23/2006 CDS_Carrier 1.
PAGE 236
freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 237
GLOBAL BYPASS CAPS. Add or subtract based on density. freescale semiconductor Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 Project: Revision: CDS_Carrier 1.
PAGE 238
CDS Carrier Schematics, Rev. 1.3 MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 239
Appendix G CDS CDC BOM This appendix provides CDC BOM for Rev. 1.1. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 240
# Board Station BOM file # date : Tuesday July 6, 2004; 12:09:48 # Variant : No_Stuff ITEM_NO COMPANY PART NO. 1 2 3 4 5 6 7 8 GEOMETRY COUNT DESCRIPTION REFERENCE led_0603 1 1 1 1 4 1 1 12 conn_184ddr_Molexdimm_vert so14 1 1 11 12 13 14 15 71243-3002 SN74LVC74APW sub SN74LV74APW 74lv08d 84740-002 981131-120-2MCF AT24C64AN-10SI-2.7 EEFUE0E221R D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 conn_184_ddr_dimm_2.5v_angled_1of2, AMP P3 sn74lvc74a.sso14, TI U2 so14 connFCI_array_10x40_sm pciconn_3.
PAGE 241
24 25 26 27 28 29 30 31 32 33 K4S561632E-TC75 LM358D LMK107F105ZA LP2995M MAX1037EKA-T MAX1813EEI MAX4372FEUK-T MBRS140T3 MBRS340T3 MCCA104K0NRT tsop54 so8 cc0603 so8 sot23_8p ssop28_pit635mm sot23_5p smb_403a smb_403 cc0402 2 1 3 1 1 1 1 1 1 140 sdram.sdr.jedec.tsop54, VAR lm358d.so8, NATSEMI cap, 1.0uF, TAIYO_YUDEN lp2995m.so8, National Semi max1037eka_t.sot23_8, Maxim max1813eei.qsop28, MAXIM max4372f.sot23_5, Maxim mbrs140t3.smb, MOT mbrs340t3.smb, MOT cap, 0.
PAGE 242
34 35 36 37 38 39 40 41 MCCA470K0NRT MCCE102KONRT MNR14-EOAB-J-390 MPC8555 Not_a_component P6880 PCA9557PW RC73L2Z000JT cc0402 cc0402 rnet1632 pbga_28x28_1mm_skt jump_2x1_1mil conn_banjo tssop16 rc0402 1 2 4 1 1 1 4 11 cap, 47pF, SMEC cap, 1000pF, muRATA rnet, 39, Rohm dracomLITE.1of9.ddr.pbga783, Motorola splice.1, PCB conn.banjo_alt, Tektronix pca9557pw.
PAGE 243
47 48 49 50 RC73L2Z124JT RC73L2Z154JT RC73L2Z200JT RC73L2Z220JT rc0402 rc0402 rc0402 rc0402 1 1 2 129 res, 120K, KOA res, 150K, KOA res, 20, KOA res, 22, KOA R324 R147 R24 R20 R318 R3 R4 R150 R151 R152 R153 R154 R155 R156 R157 R158 R159 R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213
PAGE 244
51 RC73L2Z221JT rc0402 12 res, 220, KOA 52 53 RC73L2Z223JT RC73L2Z270JT rc0402 rc0402 2 116 res, 22K, KOA res, 27, KOA R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262 R263 R264 R265 R269 R270 R271 R272 R273 R274 R275 R276 R277 R290 R298 R300 R301 R6 R7 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R279 R343 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73
PAGE 245
54 55 56 57 58 59 60 61 RC73L2Z331JT RC73L2Z333JT RC73L2Z390JT RC73L2Z391JT RC73L2Z472JT RC73L2Z563JT RC73L2Z862JT RNA4A8E102JT rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rna4a 1 1 2 1 1 1 1 4 res, 330, KOA res, 33K, KOA res, 39, KOA res, 390, KOA res, 4.7K, KOA res, 56K, KOA res, 8.6K, KOA rnet8.bussed.rna4a, 1K, AVX 62 RNA4A8E472JT rna4a 4 rnet8.bussed.rna4a, 4.7K, AVX 63 RNA4A8E472JT rna4a 7 rnpullup_3.3v.rna4a, 4.
PAGE 246
CDS CDC BOM MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 247
Appendix H CDS CPU Schematics (CDC) This appendix provides CPU board schematics for Rev. 1.1. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 248
CDC_MPC85xx freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Date Changed: 6/11/2004 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 249
Schematic Notes 1. Unless otherwise specified: All resistors are SMD0402, in ohms, 0.08W, +/-5% All capacitors are SMD0402, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: GND VCC_2.5 VCC_3.3 OVDD VCORE VCC_12 VCC_5 3.
PAGE 250
DDR Termination 13 Configuration Logic Power Supplies DDR DIMM Socket 08 12 05 Local PCI Bus Connector LocalBus Memory 20 Clocks 16 Processor X 09 LocalBus Demux/Buffer I2C Devices 19 06/10/14/15/17-19 12 Mezzanine Connector Test Access 09/11 freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85x_783 Revision: 1.
PAGE 251
160.0 mm [6.3in] 120.0 mm [4.7in] 130.0 mm [5.1in] .095 freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 LAYER 6 LAYER 7 LAYER 8 LAYER 9 LAYER 10 LAYER 11 LAYER 12 LAYER 13 LAYER 14 LAYER 15 LAYER 16 COMP PLANE SIGNAL SIGNAL PLANE SIGNAL SIGNAL PLANE PLANE SIGNAL SIGNAL PLANE SIGNAL SIGNAL PLANE SOLDER 1.0oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 1.
PAGE 252
THERMAL HEATSINK PLANE FILL 10 cm^2 on top layer VCORE Output 18A Maximum FANSINK HEADER 1A Maximum POWER SUPPLY LAYOUT RULES 1. All components in the power path (large/red bus) should be on the same layer, with area filled connections. 2. No vias or thermal reliefs allowed on power path components. 3. Ground plane connections should be made with two vias close to the component. freescale semiconductor TM Freescale Semiconductor 7700 W.
PAGE 253
CORE POWER, GUH DDR POWER TSEC POWER EVERYTHING ELSE POWER freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 254
CONFIG OPTIONS Reserved for Freescale only. freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 255
NOTE: Due to PCA9557 Issues I2C Control pins are re-arranged. See V1.0 errata or V1.1 User's Manual REMOTE CONTROL 0+1 ADDR=0x20+0x21 REMOTE CONTROL 2+3 ADDR=0x22+0x23 freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 256
CPU JTAG Header freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 257
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 258
PATH t PD = 0.25ns Compensation required on non-ECC/CB datapaths. freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 259
DIMM #1 SPD ADDR=0x51 freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 260
VTT TERMINATION PLANE Place resistors immediately behind DIMM on a plane Place capacitors behind or intermingled with resistors. Attach at mid-point of plane. freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 261
PCI PULLUPS/PULLDOWNS Not PCI compliant, yet required for non-PCI HIP. Minimal interference with actively driven signals. PCI-X SPEED ENCODING 10K installed: PCI-X + 66 MHz 10K removed: PCI-X + 133 MHz freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 262
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 263
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 264
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 265
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Date Changed: 6/11/2004 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 266
ADDRESS LATCH/BUFFER Note: The admittedly convoluted buffering scheme attempts to minimize loading on the address pins of the local SDRAM, at a small cost to the remote/ slower local bus. NOTE: LALE LENGTH LALE (LBUS_SHORT) must be 1ns (6cm) shorter than LBUS routes. CDS LOCAL BUS WIDTH Always 8 or 16 bits; see config for LB_SIZ(1) control. freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 267
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 268
BOOT SEQUENCER MEMORY ID = 0x50 MODULE ID MEMORY ID = 0x57 THERM AMPLIFIER freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 269
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 270
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 271
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 272
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 273
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 274
freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 275
GLOBAL BYPASS CAPS. Add or subtract based on density. freescale semiconductor TM Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDC_MPC85xx_783 Revision: 1.
PAGE 276
CDS CPU Schematics (CDC) MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 277
Appendix I CDS I/O Board Schematics This appendix provides CDS I/O board schematics. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 278
IOCard freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 279
Page 01 02 03 04 05 06 07 08 09 Schematic Notes 1. Unless otherwise specified: All resistors are SMD0402, in ohms, 0.08W, +/-5% All capacitors are SMD0402, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: 3.
PAGE 280
Ethernet RJ45 Connectors USB Ports CDS DC Connector 07 freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 281
#3 RJ45 SAMTE C RJ45 #4 USB USB SW1 POWER SW2 .062 freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 LAYER 6 LAYER 7 LAYER 8 LAYER 9 LAYER 10 LAYER 11 COMP PLANE SIGNAL SIGNAL PLANE SIGNAL SIGNAL PLANE SIGNAL PLANE SIGNAL 0.25oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz SIGNAL: 1 PLANE: GND SIGNAL: 3 SIGNAL: 4 PLANE: VCC_2.5 SIGNAL: 5 SIGNAL: 6 PLANE: VCC_3.
PAGE 282
freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 283
ETHERNET PORT #3 ETHERNET PORT #4 freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 284
USB PORTS #1 and #2 freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 285
EVENT 1 EVENT 2 freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 286
POWER freescale TM semiconductor Freescale Semiconductor 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_IOCard Revision: 1.
PAGE 287
Appendix J CDS uTCOM Schematics This appendix provides uTCOM schematics. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 288
uTCOM MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 1/12/2004 Engineer: Mark S.
PAGE 289
Page 01 02 03 04 05 06 07 08 09 10 11 12 Schematic Notes 1. Unless otherwise specified: All resistors are SMD0603, in ohms, +/-5% All capacitors are SMD0402, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: 3.
PAGE 290
TCOM LB Connector TCOM CPM Connector <10> <10> USB, USB Connector <11> CPM Signal Swap Area <09> ADS CPM CPLD <07-08> Logic Analyzer Banjo Headers <12> uTCOM Connector <05-06> MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 1/28/2004 Engineer: Mark S.
PAGE 291
.062 MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 LAYER 6 LAYER 7 LAYER 8 LAYER 9 LAYER 10 LAYER 11 LAYER 12 COMP PLANE SIGNAL PLANE PLANE SIGNAL SIGNAL PLANE PLANE SIGNAL PLANE SOLDER 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz 0.5oz SIGNAL: 1 PLANE: GND SIGNAL: 3 PLANE: VCC_3.
PAGE 292
MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 293
MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 294
S ch e m a tic N o te s * A D S F P G A p in o u t is id e n tica l to th e M S IL d e sig n o n th e A D S b o a rd F P G A S IG N A L S In p u ts LB_A_(29:31) LB_WE*(0) LB_GPL(2) LB_CS*(4) LB_CS*(7:6) uTCOM_RST* O u tp u ts ADS_LBBOE2* ATMEN* ATMRST* FETHRST* B id ir LB_D(0:7) DS3_TR1* DS3_RT1* DS3_TR2* DS3_RT2* ENDS3_1 ENDS3_2 TOOLREV(0:3) TOOLID(0:3) MOTOROLA JT A G TDI TMS TCLK TDO MOTOROLA INC. 7700 W.
PAGE 295
* L B e xp a n sio n co n n e cto r sig n a ls * P la ce n e a re xp a n sio n co n n e cto r * In p u ts to A D S C P L D fro m e xp a n sio n co n n e cto r * P la ce n e a r th e C P L D . * A D S C P L D in p u ts a n d o u tp u ts * P la ce n e a r th e A D S C P L D * U n u se d A D S C P L D in p u ts * P la ce n e a r th e A D S C P L D MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 296
MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 297
D o u b le ch e ck o rie n ta tio n CONNECTOR KEYSIDE ERNI023762 D 32 C 32 B 32 A 32 NC 5V 5V GND NC 5V 5V V P P _ IN (N C ) D2 GND D1 GND C2 GND C1 GND B2 GND B1 GND A2 ADDR17 A1 ADDR16 CONNECTOR KEYSIDE CONNECTOR KEYSIDE ERNI023762 D 32 C 32 B 32 A 32 PC0 GND PA0 3.3V D 31 C 31 B 31 A 31 C PM SIG N ALS PC1 D2 GND C2 PC30 PB30 D1 C1 PC31 PB31 PA1 3.
PAGE 298
MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 299
MOTOROLA MOTOROLA INC. 7700 W. Parmer Ln Austin, Texas 78729 Project: CDS_uTCOM Revision: 1.0 Date Changed: 2/18/2004 Engineer: Mark S.
PAGE 300
CDS uTCOM Schematics MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 301
Appendix K CDS Arcadia BOM This appendix provides Arcadia X3 BOM for Rev. 3.1. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 302
Board Station BOM file date : June 30, 2005; 15:09:37 Variant : No_Stuff ITEM_NO Updated on 08/19/05 Arcadia Rev X3.1 COMPANY PART NO. GEOMETRY COUNT 1 2 0603YC104JAT2A PCB_arcadia cc0603 3 102972-2 4 5 6 7 8 9 10 DESCRIPTION REFERENCE 1 12 cap, 0.1uF, AVX, 5% header_1x2 10 header.
PAGE 303
30 EMK107F224ZA cc0603 8 cap, .22uF, TAIYO_YUDEN, +80-20% 31 EXCCL4532U1 induct_4532 19 exccl4532.smd, PANASONIC 32 33 34 35 36 37 38 39 40 41 42 43 44 FPX250F-20 FTSH-113-01-L-DV-K GRM39X7R104K050AD GSP-B-S2-GG-9100 HC49SD33.333 HF30ACB453215-T IS24C02-3G LM393M LMK107F105ZA LT1117CST-3.
PAGE 304
45 46 MCCA180K0NRT MCCA270K0NRT cc0402 cc0402 2 7 cap, 18pF, SMEC, 10% cap, 27pF, SMEC, 10% 47 48 49 MCCA470K0NRT MCCE100JONRT MCR03-EZH-F-49R9 cc0402 cc0402 rc0603 5 2 4 cap, 47pF, SMEC, 10% cap, 10pF, muRATA, 5% res, 49.
PAGE 305
50 51 52 53 54 MIC2526-2 MIC29152BU MMBT3904 MNR14-EOAB-J-102 MNR14-EOAB-J-330 so8 to263_5p sot23 rnet1632 rnet1632 1 1 1 1 12 mic2526_2.so8, MICREL mic29152bu.to263_5, MICREL mmbt3904_npn.sot23, Motorola rnet, 1K, Rohm, 5% rnet, 33, Rohm, 5% 55 56 57 MPC9109FA MPC9855VF NOT_A_COMPONENT lqfp32 bga_10x10 tp_pth 1 1 9 mpc9109fa.lqfp32, Freescale mpc9855.bga_10x10, Freescale test.pth, None 58 59 60 RC73A2Z1000FT RC73A2Z1002FT RC73L2Z000JT rc0402 rc0402 rc0402 1 2 7 res, 100, SMEC, 1% res, 10.
PAGE 306
74 RC73L2Z331JT rc0402 5 res, 330, SMEC, 5% 75 76 77 RC73L2Z332JT RC73L2Z470JT RC73L2Z471JT rc0402 rc0402 rc0402 2 1 6 res, 3.3K, SMEC, 5% res, 47, SMEC, 5% res, 470, SMEC, 5% 78 RC73L2Z472JT rc0402 39 res, 4.7K, SMEC, 5% 79 80 81 82 83 RC73L2Z562JT RC73L2Z563JT RC73L2Z682JT RC73L2Z750JT RC73L2Z822JT rc0402 rc0402 rc0402 rc0402 rc0402 1 1 1 2 103 res, 5.6K, SMEC, 5% res, 56K, SMEC, 5% res, 6.8K, SMEC, 5% res, 75, SMEC, 5% res, 8.
PAGE 307
84 85 86 87 88 89 90 91 RK73H2AT1602F RM73B1JT050JF RM73B1JT100J RM73B1JT150J RM73B2ETE-100J RNA4A8E102JT RNA4A8E103JT RNA4A8E472JT rc0805 rc0603 rc0603 rc0603 rc1210 rna4a rna4a rna4a 1 4 2 1 1 3 2 14 res, 16K, KOA, 1% res, 5, KOA, 5% res, 10, KOA, 5% res, 15, KOA, 5% res, 10, KOA, 5% rnet8.bussed.rna4a, 1K, AVX, 5% rnpullup_3.3v.rna4a, 10K, AVX, 5% rnpullup_3.3v.rna4a, 4.7K, AVX, 5% 92 93 94 95 96 97 98 99 RNA4A8E472JT RNA4A8E472JT RTL8139D SG615P-14.318 SG615P-48.
PAGE 308
106 VT82C686B pbga352 1 vt82c686b.1of3.
PAGE 309
Appendix L CDS Arcadia X3 Schematics This appendix provides Arcadia X3 schematics for Rev. 3.1. MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 310
1 2 3 4 5 6 7 8 A A freescale TM semiconductor B B C C D D freescale semiconductor 1 Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 2 Project: Revision: Arcadia Date Changed: Thursday, October 20, 2005 Engineer: V3.
PAGE 311
1 2 3 4 5 6 Schematic Notes 1. A Unless otherwise specified: All resistors are SMD0603, in ohms, 0.08W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: 3.
PAGE 312
1 3 2 4 System Control PCI Config 33 MHz A PCI 33 MHz 5 Slot #5 33 MHz 3V BUS PCI 33 MHz Slot #6 <31> Isolation Buffer <06-07> 6 7 PCI 33 MHz 8 PrPMC A <32> <10-11> 33 MHz 5V BUS <20> PCI Bridge B Ethernet PCI / PCI-X 33-66 MHz IO <21-24> B VIA South Bridge USB/IDE/PS2/SER/Floppy Realtek <18-19> <13-16> System Power Supply 2.
PAGE 313
1 2 3 4 5 6 7 8 Align per Gasket #4, #21 or #40 A A ENET over Dual DIN6 USB HIPSLOT 2 HIPSLOT 1 PCI-X PCI-X PCIX 3V 64b PCIX 3V 64b B PCI 5V 32b PCI 5V 32b RTK8139 B TSI310 MPMC MPMC Expansion ATX CPLD C C Rapid Rapid IO VIA IO ATX D D freescale semiconductor 1 Freescale Semiconductor TM 7700 W. Parmer Ln Austin, Texas 78729 2 Project: Revision: Arcadia Date Changed: Thursday, October 20, 2005 Engineer: V3.
PAGE 314
1 2 VCC_12 3 VCC_12N VCC_5 VCC_3.3 2 GND1 P12V4 GND2 P12V3 VCC_5 VCC_12 VCC_HOT_5 VCC_5 7 8 VCC_5 atxpwr_2x10vert_nopeg 11 4 12 3 13 1 +3.3V_P11 +3.3V_P1 -12V_P12 +3.3V_P2 GND_P13 GND_P3 15 GND_P15 16 GND_P16 17 GND_P17 18 -5V_P18 C274 330uF C196 330uF 25V + 25V + 2 NC 5 3 R283 GND_P5 6 J22 header.1x3 ATX Chassis Header Power LED Cable POWER 4.
PAGE 315
1 3 2 4 5 VCC_3.3 K5 J6 conn.2x13 NC NC NC NC NC NC K12 1 2 L5 3 4 L12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 M6 10CM_MAX 10CM_MAX M10 M11 10CM_MAX 10CM_MAX R43 0 P14 10CM_MAX R15 10CM_MAX P13 10CM_MAX R14 10CM_MAX R16 T15 R47 + C2 10uF M7 C3 C5 0 N14 0.1uF 16V 0.1uF 16V No_Stuff P15 C9 0.1uF VCC_3.3 B A2 R44 R49 10.0K 10.
PAGE 316
1 2 3 4 6 5 7 8 U14 apa150.2of2.fbga256 A TP7 G2 TP8 G3 TP3 MPC9855_RST* 8D1 G1 TP4 G4 G13 TP1 TP2 PCIB_CLK(0:6) 9A8,11B1,13D1,18D1,22D1,31A1,32A1 G14 G15 TP6 G16 TP5 VCC_3.3 U11 133.33MHz R23 SHORT_POWER + C87 22uF <,,,annot_deleted,> <,,,annot_deleted,> 4 C93 0.1uF V3.
PAGE 317
1 2 4 3 5 6 7 8 VCC_3.3 R160 1 SHORT_POWER SHORT_POWER + C230 22uF VCC_3.3 VCC_3.3 R193 A SHORT_POWER R161 PWR SHORT_POWER rc0603 5 A1 C218 0.1uF C233 0.1uF A9 A10 B1 B2 B7 C249 B9 B10 C217 .22uF C207 0.1uF C209 0.1uF D2 D1 K6 C224 .
PAGE 318
2 1 3 4 5 6 7 8 U26 mpc9109fa.lqfp32 R182 4.7K 4 8 PWR 16 29 VCC_3.3 R158 5 7 SHORT_POWER PWR C215 22uF C219 0.1uF C220 0.1uF C225 0.1uF C231 0.1uF Q9 Q10 Q11 Q12 Q13 Q14 VCCO_1 VCCO_2 VCCO_3 VCCI_1 VCCI_2 C232 0.1uF 2 + 21 Q4 Q5 Q6 Q7 Q8 LVCMOS_CLK_SEL GNDI SHORT_POWER LVCMOS_CLK GNDO_3 GNDO_4 3 VCC_3.
PAGE 319
1 2 4 3 5 6 7 8 VCC_3.3 U33 74lvt244.tssop20 LEDS(7:0) 2 0 A 1 4 2 6 3 8 1 VCC_HOT_3.3 D15 R268 4 11 5 13 Green 6 15 HOT_3V 7 17 1CM_MAX 220 1 19 R298 D17 1Y3 1A4 1Y4 16 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 220 1CM_MAX L2_ARC 7 R241 5 3 L3_ARB L4_BOOT 1CM_MAX 74lvc1g125.sc70 R237 R266 4 1CM_MAX 74lvc1g125.sc70 220 R236 CLK 1CM_MAX 220 L8_PCIB VCC_3.3 PWRGD D16 SW2 sw.8spst.
PAGE 320
1 2 3 4 6 5 8 7 TMS ARC_TDO TCK 6B1,23C1,26A8,27A8,28A8,30A8,31A8,32A8 6B1 6B1,23C1,26A8,27A8,28A8,30A8,31A8,32A8 A A PCIB4_GNT*(1:5) PCIB4_IRDY* PCIB4_LOCK* J8 VCC_12N 120521-1 conn.2x32.
PAGE 321
1 2 3 4 5 6 7 8 A A VCC_5 J9 120521-1 conn.2x32.ieee1386 NC 2 3 4 5 6 7 64-bit PrPMC connector used for additional 5V power only - 64bit PCI not supported.
PAGE 322
3 4 5 Y5 smdxtal_32kHz 4 2CM_MAX C263 10pF C254 0.1uF C99 0.1uF C272 0.1uF C273 0.
PAGE 323
1 2 3 5 4 6 7 8 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K TP20 VCC_5 3 Y4 V3 4 W3 3 Y3 2 W2 1 Y2 0 Y1 R248 L3 R253 D3 R262 R261 E2 R250 R249 M1 DRQ0 SA15 SD6 SA14 PCI Super IO SA13 SD4 SA12 SD3 SA11 SD2 SA10 SD1 SA9 SD0 SA8 SA7 4.7K RN23 4.7K RN23 1 B D1 2 VCC_ VCC_ 3.3 3.
PAGE 324
1 2 3 4 5 6 7 VCC_5 VCC_5 VCC_5 IDERST* 6D1 8 IRQ14 P_80P R297 A PDA2 SDA1 SLCT SDA0 1 U19 0 R271 R279 R272 10K 1K Y20 1K R274 W19 2 3 4 5 6 7 7 8 5 6 7 8 7 0 1 6 RN39 33 4 3 2 1 3 1 1 5 2 11 7 3 15 13 2 4 17 9 8 6 10 16 12 14 18 3 4 9 8 5 2 10 6 RN40 1 11 7 2 33 8 3 1 5 6 7 7 8 7 4 RN33 33 1 3 1 8 6 9 4 2 6 5 10 16 7 18 12 14 2 1 3 20 33 4 shrouded 33 8 17 19 21 23 25 header_2x20_shrouded 22
PAGE 325
1 2 3 5 4 VCC_3.3 6 8 7 VCC_12 VCC_HOT_3.3 A R296 R285 4.7K 4.7K 13D8 BAS16LT1 CR6 BAS16LT1 VBAT_3V 13D1 J26 conn.battery A FANSPD1 FANSPD2 13D8 CR7 1 R295 J25 2 1 C299 0.1uF 100 3 1 - + 1CM_MAX + C302 0.1uF 2 2 C301 10uF R299 100 1CM_MAX J29 header.1x3 3 1CM_MAX 1 J27 2 VCC_HOT_3.3 3 R243 4.7K R244 PWRSW* 5C8 PWRBTN* 13D1 47 C276 0.1uF B B VCC_HOT_5 VCC_HOT_3.3 R260 4.
PAGE 326
1 3 2 4 5 6 7 8 A A VCC_5 VCC_5 VCC_3.3 U1 lt1331cg.ssop28 SYS LINE TXD1 DTR1 RTS1 14C8 14C8 14C8 25 23 19 NC DCD1 RXD1 RI1 CTS1 DSR1 14C8 14C8 14C8 14C8 14C8 16 24 21 20 18 C13 0.1uF C12 0.1uF 1CM_MAX 1CM_MAX C15 0.1uF C14 0.1uF 1CM_MAX D2OUT D3IN D3OUT R1IN R2OUT R2IN R3OUT R3IN R4OUT R4IN R5IN 4 26 27 C1+ VCC C1- VL C2+ V+ V- C2GND NC 15 NC VCC_5 2CM_MAX 7 2CM_MAX 2CM_MAX J1 conn.db9.plug.
PAGE 327
1 2 3 4 5 6 8 7 28 91 27 92 26 93 25 94 24 95 23 100 22 1 21 3 20 4 19 5 18 B 8 17 9 16 10 15 23 14 24 13 25 12 26 11 27 10 28 9 29 8 30 7 33 6 36 5 37 4 38 3 41 2 42 1 44 0 45 R197 99 1CM_MAX 11A8,13C1,20B1,31A1,32A1 11D1,13C1,20B1,31A1,32A1 11B1,13C1,20B1,31A1,32A1 11B8,13C1,20B1,31A1,32A1 11C1,13C1,20B1,31B8,32B8 C 3 98 2 11 1 21 0 32 PCIB4_FRAME* PCIB4_IRDY* PCIB4_TRDY* PCIB4_DEVSEL* PCIB4_STOP* PCIB4_PAR PCIB4_PERR* PCIB4_SER
PAGE 328
2 3 RN1 U3 mic2526_2.so8 3 7 SHORT_POWER 5 1 8 SHORT_POWER SHORT_POWER SHORT_POWER FB8 OC0* OC1* 2 ENA FLGA 4 A 7 FB9 OUTA OUTB C44 0.1uF 6 2 8 IN 5 4.7K VCC_5 4 VCC _5V 4.7K VCC _5V RN1 1 3 ENB FLGB 14A1 14A1 A GND + 6 C80 47uF + C66 47uF J4 conn.rj45led_over_dualusb.
PAGE 329
1 2 3 4 5 6 7 8 A A VCC_5 C131 0.
PAGE 330
1 2 4 3 5 6 7 8 VCC_3.3 PBRIDGE_EN* 10D8 U20 74cbtlv1g125dbv.so5 VCC_3.3 3 1 OE GND 2 8.2K B 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K R59 4 A R60 4.7K A 28 5 33 VCC VCC_3.3 A U23 tsi310.1of4.pci_p.
PAGE 331
1 2 3 4 5 6 7 8 VCC_3.3 U19 74cbtlv1g125dbv.so5 SBRIDGE_EN* 10D8 VCC_3.3 1 3 OE GND 2 4 A B 5 8.2K 8.2K R58 4.
PAGE 332
1 2 3 4 5 7 6 8 A A 8.2K R122 8.2K 8.2K R62 VCC_3.3 U23 R68 tsi310.3of4.control.pbga304 CONTROL VCC_3.3 PWR PCI Bridge Options SW1 sw.8spst.cts RN5 15 T21 3 14 Y22 8 16 2 6 5 12 6 11 7 10 8 9 2 3 4 5 AC22 V3 2CM_MAX C6 E2 1 10 AA18 13 4 B G2 1 7 9 330 AC7 8 7 6 5 4 3 2 1 RN3 2.
PAGE 333
1 2 3 4 5 7 6 8 VCC_5 VCC_2.5 CR1 CR2 CR3 MBRS360T3 MBRS360T3 MBRS360T3 1 2 1 2 2 PWR R66 10 1 rc1210 smc_403 A smc_403 smc_403 A U21 mic29152bu.to263_5 1 4 IN1 OUT1 IN2 OUT2 3 + SHORT_POWER 5 1CM_MAX GND2 GND1 2 R70 U23 tsi310.4of4.power.pbga304 6 470 + C154 22uF R73 C153 22uF 16V 470 16V POWER TSI310A-133CE F6 <,,,annot_deleted,> 2CM_MAX HF30ACB453215-T 70 ohms 300mA B P_AVDD C155 0.
PAGE 334
1 2 3 4 5 6 7 8 P4 conn.amp.HM-Zd.40pr.plug.vert VCC_3.
PAGE 335
1 2 3 4 5 6 7 8 VCC_HOT_3.3 SLOT2 pcix_conn_univ_64bit_block A PCIA_CLK(0:5) PCIA_PCIRST* 7B1,8B8,21D1,27A1,28A1,30A1 6D1,21D1,27A1,28A1,30A1 3 A B16 B9 CLK PRSNT1 A15 NC B11 PRSNT2 RST NC A14 P3.
PAGE 336
1 2 3 4 5 7 6 8 VCC_HOT_3.3 SLOT3 pcix_conn_univ_64bit_block A PCIA_CLK(0:5) PCIA_PCIRST* 7B1,8B8,21D1,26A1,28A1,30A1 6D1,21D1,26A1,28A1,30A1 2 ML-3 A B16 B9 CLK PRSNT1 A15 NC B11 PRSNT2 RST NC A14 P3.
PAGE 337
1 2 3 4 5 6 7 8 VCC_HOT_3.3 SLOT4 pcix_conn_univ_64bit_block A PCIA_CLK(0:5) PCIA_PCIRST* 7B1,8B8,21D1,26A1,27A1,30A1 6D1,21D1,26A1,27A1,30A1 1 A B16 B9 CLK PCI_A1 A15 PCIA_FRAME* PCIA_DEVSEL* PCIA_IRDY* PCIA_TRDY* PCIA_STOP* PCIA_LOCK* PCIA_PERR* PCIA_SERR* PCI_A1 A34 PCI_A1 B37 PCI_A1 B42 SMBCLK SMBDAT PCI_A1 A40 PRSNT1 NC B11 PRSNT2 RST NC A14 P3.
PAGE 338
1 2 3 4 6 5 7 8 P3 conn.amp.HM-Zd.40pr.plug.vert VCC_3.
PAGE 339
1 2 3 4 5 6 7 8 VCC_HOT_3.3 SLOT5 pcix_conn_univ_64bit_block A PCIA_CLK(0:5) PCIA_PCIRST* 7B1,8B8,21D1,26A1,27A1,28A1 6D1,21D1,26A1,27A1,28A1 0 A B9 B16 CLK PRSNT1 NC B11 A15 RST PRSNT2 NC A14 P3.
PAGE 340
1 2 3 4 5 6 7 8 SLOT6 A PCIB_CLK(0:6) PCIB_PCIRST* 7A1,9A8,11B1,13D1,18D1,22D1,32A1 6D1,11C1,18D1,32A1 11B1,13C1,18C1,20B1,32A1 11B1,13C1,18C1,20B1,32A1 11A8,13C1,18C1,20B1,32A1 11D1,13C1,18C1,20B1,32A1 11B8,13C1,18C1,20B1,32A1 11A8,20B1,32A1 11D1,18C1,20B1,32B1 11C8,13C1,18C1,20B1,32B1 13B8,16C8,26B1,27B1,28B1,30B1,32B1 13B8,16C8,26B1,27B1,28B1,30B1,32B1 11D1,32B1 5 11B1,13D1,18C1,20C1,32B1 B16 PCI_B4 A15 PCI_B4 A34 PCI_B4 B37 PCI_B4 B42 SMBCLK SMBDAT PCIB4_M66EN PCI_B4 A40 PCI_
PAGE 341
1 2 3 4 5 6 7 8 SLOT7 A PCIB_CLK(0:6) PCIB_PCIRST* 7A1,9A8,11B1,13D1,18D1,22D1,31A1 6D1,11C1,18D1,31A1 11B1,13C1,18C1,20B1,31A1 11B1,13C1,18C1,20B1,31A1 11A8,13C1,18C1,20B1,31A1 11D1,13C1,18C1,20B1,31A1 11B8,13C1,18C1,20B1,31A1 11A8,20B1,31A1 11D1,18C1,20B1,31B1 11C8,13C1,18C1,20B1,31B1 13B8,16C8,26B1,27B1,28B1,30B1,31B1 13B8,16C8,26B1,27B1,28B1,30B1,31B1 11D1,31B1 6 A34 SMBCLK SMBDAT PCIB4_M66EN A40 11B1,13D1,18C1,20C1,31B1 PRSNT1 NC B11 5V: 145154-1 RST PCIB4_FRAME* PCIB4_DEVSEL* PC
PAGE 342
VCC_5 VCC_3.3 C186 VCC_12 C139 47uF 47uF C190 C115 C68 47uF C48 0.1uF 0.1uF 0.1uF 0.1uF + 47uF C53 + 47uF C61 + 47uF C140 + 47uF 47uF 8 A C182 47uF 7 C39 47uF 47uF 47uF C142 C177 0.1uF 0.1uF 0.1uF 0.1uF C194 C174 C81 C156 C193 6 VCC_12N C70 + C42 5 + VCC_12N C75 + + VCC_12 C113 + VCC_3.3 C58 + VCC_5 A 4 + 3 2 + 1 C146 0.1uF 0.1uF 0.1uF 0.1uF C89 C148 C203 C114 0.1uF 0.1uF 0.1uF 0.
PAGE 343
Glossary The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this reference manual. A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible most-significant byte. Atomic access.
PAGE 344
Glossary Bus clock. Clock that causes the bus state transitions. Bus master. The owner of the address or data bus; the device that initiates or requests the transaction. C Cache. High-speed memory containing recently accessed data or instructions (subset of main memory). Cache block. A small region of contiguous memory that is copied from memory into a cache. The size of a cache block may vary among processors; the maximum block size is one page.
PAGE 345
Glossary Context synchronization. An operation that ensures that all instructions in execution complete past the point where they can produce an exception, that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain events occur (such as an exception). Copy-back operation.
PAGE 346
Glossary Flush. An operation that causes a cache block to be invalidated and the data, if modified, to be written to memory. G General-purpose register (GPR). Any of the 32 registers in the general-purpose register file. These registers provide the source operands and destination results for all integer data manipulation instructions. Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory. Gigabit media-independent interface (GMII) sublayer.
PAGE 347
Glossary Instruction latency. The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction. K Kill. An operation that causes a cache block to be invalidated without writing any modified data to memory. L Latency. The number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction. L2 cache. Level-2 cache. See Secondary cache. Least-significant bit (lsb).
PAGE 348
Glossary Memory coherency. An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory. Memory consistency. Refers to agreement of levels of memory with respect to a single processor and system memory (for example, on-chip cache, secondary cache, and system memory). Memory management unit (MMU).
PAGE 349
Glossary Outbound ATMU windows. Mappings that perform address translations from local 32-bit address space to the address spaces of RapidIO or PCI/PCI-X, which may be much larger than the local space. Outbound ATMU windows also map attributes such as transaction type or priority level. P Packet. A unit of binary data that can be routed through a network. Sometimes packet is used to refer to the frame plus the preamble and start frame delimiter (SFD). Page. A region in memory.
PAGE 350
Glossary Physical medium dependent (PMD) sublayer. Sublayer responsible for signal transmission. The typical PMD functionality includes amplifier, modulation, and wave shaping. Different PMD devices may support different media. Physical memory. The actual memory that can be accessed through the system’s memory bus. Pipelining.
PAGE 351
Glossary RapidIO. High-performance, packet-switched, interconnect architecture that provides reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. Designed to be compatible with integrated communications processors, host processors, and networking digital signal processors, Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the condition register (CR) to reflect the result of the operation. Reconciliation sublayer.
PAGE 352
Glossary Set-associative. Aspect of cache organization in which the cache space is divided into sections, called sets. The cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache. Slave. The device addressed by a master device. The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure. Snooping.
PAGE 353
Glossary Transfer termination. Signal that refers to both signals that acknowledge the transfer of individual beats (of both single-beat transfer and individual beats of a burst transfer) and to signals that mark the end of the tenure. Translation lookaside buffer (TLB). A cache that holds recently-used page table entry. U User mode. The operating state of a processor used typically by application software.
PAGE 354
Glossary MPC8555E Configurable Development System Reference Manual, Rev.
PAGE 355
PAGE 356
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.