Specifications

MPC8555E Configurable Development System Reference Manual, Rev. 1
Glossary-4 Freescale Semiconductor
Glossary
Flush. An operation that causes a cache block to be invalidated and the data, if modified,
to be written to memory.
G General-purpose register (GPR). Any of the 32 registers in the general-purpose register
file. These registers provide the source operands and destination results for all
integer data manipulation instructions. Integer load instructions move data from
memory to GPRs and store instructions move data from GPRs to memory.
Gigabit media-independent interface (GMII) sublayer. Sublayer that provides a
standard interface between the MAC layer and the physical layer for 1000-Mbps
operation. It isolates the MAC layer and the physical layer, enabling the MAC
layer to be used with various implementations of the physical layer.
Guarded. The guarded attribute pertains to out-of-order execution. When a page is
designated as guarded, instructions and data cannot be accessed out-of-order.
H Harvard architecture. An architectural model featuring separate caches and other
memory management resources for instructions and data.
I IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that
defines operations and representations of binary floating-point numbers.
Illegal instructions. A class of instructions that are not implemented for a particular
processor. These include instructions not defined by the architecture. In addition,
for 32-bit implementations, instructions that are defined only for 64-bit
implementations are considered to be illegal instructions. For 64-bit
implementations instructions that are defined only for 32-bit implementations are
considered to be illegal instructions.
Implementation. A particular processor that conforms to the architecture, but may differ
from other architecture-compliant implementations (for example, in design,
feature set, and implementation of optional features).
Inbound ATMU windows. Mappings that perform address translation from the external
address space to the local address space, attach attributes and transaction types to
the transaction, and map the transaction to its target interface.
Inter-packet gap. The gap between the end of one Ethernet packet and the beginning of
the next transmitted packet.
Integer unit. An execution unit in the core responsible for executing integer instructions.
In-order. An aspect of an operation that adheres to a sequential model. An operation is
said to be performed in-order if, at the time that it is performed, it is known to be
required by the sequential execution model. See Out-of-order.