Datasheet
M393B5270DH0-CF809/CH909/CK009/CMA09
Organization : 512M x 72
Composition : 512M x 4 * 18ea
Used component part # : K4B2G0446D-HCF8/HCH9/HCK0/HCMA
# of rows in module : 1 Row
# of banks in component : 8 Banks
Feature : 30mm height & double sided component
Refresh : 8K/64ms
Bin Sort : F8(DDR3 1066@CL=7), H9(DDR3 1333@CL=9), K0(DDR3 1600@CL=11), MA(DDR3 1866@CL=13)
RCD Vendor and Revision : Inphi UV GS02
Byte
#
Function Described
Function Supported Hex Value
Note
CF809 CH909 CK009 CMA09 CF809 CH909 CK009 CMA09
0
Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage CRC coverage 0~116Byte, SPD Byte
Total :256Byte, SPD Byte Use :
176Byte
92h
1 SPD Revision Version 1.1 11h
2 Key Byte / DRAM Device Type DDR3 SDRAM 0Bh
3 Key Byte / Module Type Registered DIMM 01h
4 SDRAM Density and Banks 2Gb 8banks 03h
5 SDRAM Addressing Row : 15, Column : 11 1Ah
6 Module Nominal Voltage, VDD 1.5V only 00h
7 Module Organization 1Rank / x4 00h
8 Module Memory Bus Width ECC, 64bit 0Bh
9 Fine Timebase Dividend and Divisor 1ps 11h
10 Medium Timebase Dividend 1/8 (0.125ns) 01h
11 Medium Timebase Divisor 1/8 (0.125ns) 08h
12 SDRAM Minimum Cycle Time (tCKmin) 1.875ns 1.5ns 1.25ns 1.071ns 0Fh 0Ch 0Ah 09h
13 Reserved Reserved 00h
14
CAS Latencies Supported, Least Significant Byte
6, 7, 8
6, 7, 8,
9
6, 7, 8,
9 , 10,
11
6, 7, 8,
9 , 10,
11, 13
1Ch 3Ch FCh FCh
15
CAS Latencies Supported, Most Significant Byte
6, 7, 8
6, 7, 8,
9
6, 7, 8,
9 , 10,
11
6, 7, 8,
9 , 10,
11, 13
00h 00h 00h 02h
16 Minimum CAS Latency Time(tAAmin) 13.125ns 69h
17 Minimum Write Recovery Time (tWRmin) 15ns 78h
18 Minimum RAS# to CAS# Delay Time (tRCDmin) 13.125ns 69h
19 Minimum Row Active to Row Active Delay Time (tRRDmin) 7.5ns 6ns 6ns 5ns 3Ch 30h 30h 28h
20 Minimum Row Precharge Time (tRPmin) 13.125ns 69h
21 Upper Nibbles for tRAS and tRC - 11h
22 Minimum Active to Precharge Time (tRASmin), Least Significant Byte 37.5ns 36ns 35ns 34ns 2Ch 20h 18h 10h
23 Minimum Active to Active/Refresh Time (tRCmin), Least Significatn Byte 50.625ns 49.125ns 48.125ns 47.125ns 95h 89h 81h 79h
24 Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte 160ns 00h
25 Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte 160ns 05h
26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 7.5ns 3Ch
27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 7.5ns 3Ch
28 Upper Nibble for tFAW 37.5ns 30ns 30ns 27ns 01h 00h 00h 00h
29 Minimum Four Activate WIndow Delay Time (tFAWmin), Least Significant Byte 37.5ns 30ns 30ns 27ns 2Ch F0h F0h D8h
30 SDRAM Output Drivers supported DLL off Mode, RZQ/6, RZQ/7 83h
31 SDRAM Thermal and Refresh Options No ODTS, No ASR 01h
32 Module Thermal Sensor with TS 80h
33 SDRAM Device Type Standard Monolithic DRAM Device 00h
34 Fine Offset for SDRAM Minimum Cycle Time(tCKmin) 1.875ns 1.5ns 1.25ns 1.071ns 00h 00h 00h CAh
35 Fine Offset for Minimum CAS Latency Time(tAAmin) 13.125ns 00h
SERIAL PRESENCE DETECT
NOV. 2010