Datasheet

Rev. 1.0 July 2008
DDR2 SDRAM
RDIMM
19 of 26
(Refer to notes for informations related to this table at the component datasheet)
Parameter Symbol
DDR2-800 DDR2-667
Units
Notes
min max min max
DQ output access time from CK/CK tAC -400 400 -450 450 ps 40
DQS output access time from CK/CK tDQSCK -350 350 -400 400 ps 40
Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
Average clock LOW pulse width tCL(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
CK half pulse period tHP
Min(tCL(abs),
tCH(abs))
x
Min(tCL(abs),
tCH(abs))
x ps 37
Average clock period tCK(avg) 2500 8000 3000 8000 ps 35,36
DQ and DM input hold time tDH(base) 125 x 175 x ps 6,7,8,21,28,31
DQ and DM input setup time tDS(base) 50 x 100 x ps 6,7,8,20,28,31
Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK(avg)
DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK(avg)
Data-out high-impedance time from CK/CK tHZ x tAC(max) x tAC(max) ps 18,40
DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18,40
DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18,40
DQS-DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 ps 13
DQ hold skew factor tQHS x 300 x 340 ps 38
DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps 39
DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 -0.25 0.25 tCK(avg) 30
DQS input HIGH pulse width tDQSH 0.35 x 0.35 x tCK(avg)
DQS input LOW pulse width tDQSL 0.35 x 0.35 x tCK(avg)
DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK(avg) 30
DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK(avg) 30
Mode register set command cycle time tMRD 2 x 2 x nCK
MRS command to ODT update delay tMOD 0 12 0 12 ns 32
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10
Write preamble tWPRE 0.35 x 0.35 x tCK(avg)
Address and control input hold time tIH(base) 250 x 275 x ps 5,7,9,23,29
Address and control input setup time tIS(base) 175 x 200 x ps 5,7,9,22,29
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42
Activate to activate command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4,32
Activate to activate command period for 2KB page size products tRRD 10 x 10 x ns 4,32
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)