Datasheet

Rev. 1.0 July 2008
DDR2 SDRAM
RDIMM
21 of 26
(Refer to notes for informations related to this table at the component datasheet)
Parameter Symbol
DDR2-533 DDR2-400
Units Notes
min max min max
DQ output access time from CK/CK tAC -500 500 -600 600 ps
DQS output access time from CK/CK tDQSCK -450 450 -500 500 ps
CK HIGH pulse width tCH 0.45 0.55 0.45 0.55 tCK
CK LOW pulse width tCL 0.45 0.55 0.45 0.55 tCK
CK half pulse period tHP Min(tCL, tCH) x Min(tCL, tCH) x ps 11,12
Clock cycle time, CL=x tCK 3750 8000 5000 8000 ps 15
DQ and DM input hold time (differential strobe) tDH(base) 225 x 275 x ps 6,7,8,21,28
DQ and DM input setup time (differential strobe) tDS(base) 100 x 150 x ps 6,7,8,20,28
DQ and DM input hold time (single-ended strobe) tDH1(base) -25 x 25 x ps 6,7,8,26
DQ and DM input setup time (single-ended strobe) tDS1(base) -25 x 25 x ps 6,7,8,25
Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK
DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK
Data-out high-impedance time from CK/CK tHZ x tAC(max) x14 tAC(max) ps 18
DQS(/DQS) low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18
DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18
DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps 13
DQ hold skew factor tQHS x 400 x 450 ps 12
DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps
DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 -0.25 0.25 tCK
DQS input HIGH pulse width tDQSH 0.35 x 0.35 x tCK
DQS input LOW pulse width tDQSL 0.35 x 0.35 x tCK
DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK
DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK
Mode register set command cycle time tMRD 2x2xtCK
MRS command to ODT update delay tMOD 0 12 0 12 ns
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10
Write preamble tWPRE 0.35 x 0.35 x tCK
Address and control input hold time tIH(base) 375 x 475 x ps 5,7,9,23
Address and control input setup time tIS(base) 250 x 350 x ps 5,7,9,22
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK 19
Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4
Active to active command period for 2KB page size products tRRD 10 x 10 x ns 4
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)