S3C2440A 32-BIT RISC MICROPROCESSOR USER'S MANUAL PRELIMINARY Revision 0.
S3C2440A RISC MICROPROCESSOR 1 PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components. The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR FEATURES Architecture NAND Flash Boot Loader • Integrated system for hand-held devices and general embedded applications. • Supports booting from NAND flash memory. • 4KB internal buffer for booting. • 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. • Supports storage memory for NAND flash memory after booting. • Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW FEATURES (Continued) Interrupt Controller • 60 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera), 1 AC97 • Level/Edge mode on external interrupt source • Programmable polarity of edge and level • Supports Fast Interrupt request (FIQ) for very urgent interrupt request gray levels, 256 colors and 4096 colors for STN LCD • Suppor
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR FEATURES (Continued) A/D Converter & Touch Screen Interface • DMA burst4 access support(only word transfer) • 8-ch multiplexed ADC • • Max. 500KSPS and 10-bit Resolution Compatible with SD Memory Card Protocol version 1.0 • Internal FET for direct Touch screen interface • Compatible with SDIO Card Protocol version 1.0 • 64 Bytes FIFO for Tx/Rx • Compatible with Multimedia Card Protocol version 2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM ARM920T IPA[31:0] Instruction CACHE (16KB) Instruction MMU External Coproc Interface C13 IVA[31:0] JTAG ID[31:0] ARM9TDMI Processor core (Internal Embedded ICE) AMBA Bus I/F CP15 Write Buffer DD[31:0] DVA[31:0] DVA[31:0] C13 Data MMU DPA[31:0] LCD CONT. LCD DMA USB Host CONT. ExtMaster NAND Ctrl. NAND Flash Boot Loader Clock Generator (MPLL) Data CACHE (16KB) A H B WriteBack PA Tag RAM WBPA[31:0] BUS CONT.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR PIN ASSIGNMENTS U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 BOTTOM VIEW Figure 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-1.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW NOTE: 1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master. 2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode. 3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register. 4. AI/AO means analog input/analog output. 5. P, I, and O mean power, input and output respectively. 6. The I/O state @nRESET shows the pin status in the @nRESET duration below.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS. Input (I)/Output (O) Type Descriptions d12i(vdd12ih) 1.2V Vdd for alive power d12c(vdd12ih_core), si(vssih) 1.2V Vdd/Vss for internal logic d33o(vdd33oph), so(vssoph) 3.3V Vdd/Vss for external logic d33th(vdd33th_abb) ,sth(vssbbh_abb) 3.3V Vdd/Vss for analog circuitry d12t(vdd12t_abb), st(vssbb_abb) 1.2V Vdd/Vss for analog circuitry drtc(vdd30th_rtc) 3.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW SIGNAL DESCRIPTIONS Table 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6) Signal Input/Output Descriptions Bus Controller OM[1:0] I OM[1:0] sets S3C2440A in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during RESET cycle.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-3.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6) Signal Input/Output Descriptions UART RxD[2:0] I UART receives data input TxD[2:0] O UART transmits data output nCTS[1:0] I UART clear to send input signal nRTS[1:0] O UART request to send output signal UEXTCLK I External clock input for UART ADC AIN[7:0] AI ADC input[7:0]. If it isn’t used pin, it has to be Low (Ground).
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6) Signal Input/Output Description SPI SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6) Signal Input/Output Description Reset, Clock & Power XTOpll AO Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, it has to be a floating pin. MPLLCAP AI Loop filter capacitor for main clock.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6) Signal Input/Output Description Power VDDalive P S3C2440A reset block and port status register VDD. It should be always supplied whether in normal mode or in Sleep mode. VDDiarm P S3C2440A core logic VDD for ARM core. VDDi P S3C2440A core logic VDD for Internal block. VSSi/VSSiarm P S3C2440A core logic VSS VDDi_MPLL P S3C2440A MPLL analog and digital VDD.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW S3C2440A SPECIAL REGISTERS Table 1-4. S3C2440A Special Registers (Sheet 1 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 2 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 3 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 4 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 5 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 6 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 7 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 8 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 9 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 10 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 11 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 12 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 13 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 14 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2440A RISC MICROPROCESSOR 2 PROGRAMMER'S MODEL PROGRAMMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of the two states: • ARM state which executes 32-bit, word-aligned ARM instructions • THUMB state is a state which can execute 16-bit, halfword-aligned THUMB instructions.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. Higher Address Word Address 31 Lower Address 24 23 16 15 8 7 0 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 Most significant byte is at lowest address.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM program execution state • FIQ (fiq): Designed to support a data transfer or channel process • IRQ (irq): Used for general-purpose interrupt handling • Supervisor (svc): Protected mode for the operating system • Abort mode (abt): Entered after a data or instruction prefetch abort • System (sys): A privileged user mode for the operating system • Undefined (und)
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR ARM State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Abort R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The relationship between ARM and THUMB state registers are as below:• THUMB state R0-R7 and ARM state R0-R7 are identical • THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical • THUMB state SP maps onto ARM state R13 • THUMB state LR maps onto ARM state R14 • The THUMB state Program Counter maps onto the ARM state Program Counter (R15) ARM state R0 R1 R2 R3 R4 R5 R6 R7 R0 R1
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (“Hi registers”) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register and from a Hi register to a Lo register, using special variants of the MOV instruction.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM state registers 10000 User R7..R0, LR, SP PC, CPSR R14..R0, PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq 10010 IRQ R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq 10011 Supervisor R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc R12..
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL Software Interrupt The Software Interrupt Instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI. NOTES nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq).
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR NOTES 2-16
S3C2440A RISC MICROPROCESSOR 3 ARM INSTRUCTION SET ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The following figure shows the ARM instruction set.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR NOTES Some instruction codes are not defined but does not cause Undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. INSTRUCTION SUMMARY Table 3-1.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3-1.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Examples ADR R0, Into_THUMB + 1 Generate branch target address and set bit 0 high – hence it comes in THUMB state BX R0 Branch and change to THUMB state. CODE16 Assemble subsequent code as Into_THUMB THUMB instructions ADR R5, Back_to_ARM Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state. BX R5 Branch and change back to ARM state.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 28 27 Cond 25 24 23 101 0 L Offset [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition Field Figure 3-3. Branch Instructions Branch instruction contains a signed 2's complement 24 bit offset.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX Items in “{}” are optional. Items in “<>” must be present. B{L}{cond} {L} Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction. {cond} A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be used. The destination.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations can be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may contain an immediate field in the instruction, or in the bottom byte of another register (other than R15).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 31 5 4 0 Contents of Rm carry out 0 0 0 0 0 Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9. 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3-9.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX • MOV,MVN (single operand instructions). {cond}{S} Rd, • CMP,CMN,TEQ,TST (instructions which do not produce a result). {cond} Rn, • AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC {cond}{S} Rd,Rn, where: Rm{,} or,<#expression> {cond} A two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET MRS (transfer PSR contents to a register) 31 28 27 23 22 21 Ps 00010 Cond 16 15 001111 12 11 0 Rd 000000000000 [15:12] Destination Register [22] Source PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MSR (transfer register contents to PSR) 31 28 27 23 22 21 00010 Cond 12 11 Pd 101001111 4 3 00000000 0 Rm [3:0] Source Register [22] Destination PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MSR (transfer regis
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM920T programs and future processors, the following rules should be observed: • The reserved bits should be preserved while changing the value in a PSR.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX • MRS - transfer PSR contents to a register MRS{cond} Rd, • MSR - transfer register contents to PSR MSR{cond} ,Rm • MSR - transfer register contents to PSR flag bits only MSR{cond} ,Rm The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR OPERAND RESTRICTIONS • R15 must not be used as an operand or as a destination register. • RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply & Accumulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply Long 32 x 32 = 64 SMLAL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply & Accumulate Long 32 x 32 + 64 = 64 where: {cond} Two-character condition mnemonic.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR memory register A A A+3 24 24 B A+2 B 16 16 C A+1 C 8 8 D A D 0 0 LDR from word aligned address memory register A A 24 A+3 B 16 A+2 C 16 C 8 A+1 D A 24 B 8 D 0 0 LDR from address offset by 2 Figure 3-15.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). While using R15 as the base register, you must remember it contains an address of 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the instruction plus 12.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX {cond}{B}{T} Rd, where: LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. {B} If B is present then byte transfer, otherwise word transfer {T} If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged mode for the transfer cycle.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES STR R1,[R2,R4]! STR LDR LDR LDREQB R1,[R2],R4 R1,[R2,#16] R1,[R2,R3,LSL#2] R1,[R6,#5] STR PLACE R1,PLACE ; ; ; ; ; ; ; ; Store R1 at R2+R4 (both of which are registers) and write back address to R2. Store R1 at R2 and write back R2+R4 to R2. Load R1 from contents of R2+16, but don't write back. Load R1 from contents of R2+R3*4. Conditionally load byte at R6+5 into R1 bits 0 to 7, filling bits 8 to 31 with zeros.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
S3C2440A RISC MICROPROCESSOR 31 28 27 Cond ARM INSTRUCTION SET 25 24 23 22 21 20 19 000 P U 1 W L 16 15 Rn 12 11 Rd 8 7 6 5 4 3 Offset 1 S H 1 0 Offset [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfword 1 = Signed byte 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into bas
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below. Signed byte and halfword loads The S bit controls the loading of sign-extended data. When S=1 the H bit selects between Bytes (H=0) and Halfwords (H=1).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX {cond} Rd, LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2.. H Transfer halfword quantity SB Load sign extended byte (Only valid for LDR) SH Load sign extended halfword (Only valid for LDR) Rd An expression evaluating to a valid register number.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES LDRH STRH LDRSB LDRNESH HERE STRH FRED R1,[R2,-R3]! ; ; ; R3,[R4,#14] ; R8,[R2],#-223 ; ; R11,[R0] ; ; ; R5, [PC,#(FRED-HERE-8)]; Load R1 from the contents of the halfword address contained in R2-R3 (both of which are registers) and write back address to R2 Store the halfword in R3 at R14+14 but don't write back. Load R8 with the sign extended contents of the byte address contained in R2 and write back R2-223 to R2.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 0x100C 0x100C R1 Rn 0x1000 0x1000 0x0FF4 0x0FF4 2 1 0x100C Rn R5 R1 R7 R5 R1 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 3 4 Figure 3-20. Pre-Increment Addressing Rn 0x100C 0x100C 0x1000 0x1000 R1 0x0FF4 0x0FF4 2 1 0x100C 0x100C 0x1000 R7 R5 R1 R5 R1 0x0FF4 3 0x0FF4 Rn 4 Figure 3-21.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET Rn 0x100C 0x100C 0x1000 0x1000 R1 0x0FF4 0x100C 0x100C 0x1000 R5 R1 0x0FF4 2 1 0x0FF4 0x1000 Rn 3 R7 R5 R1 0x0FF4 4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction it depends on R15 is available in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX {cond} Rn{!},{^} where: {cond} Two character condition mnemonic. See Table 3-2. Rn An expression evaluating to a valid register number A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). {!} If present requests write-back (W=1), otherwise W=0. {^} If present set S bit to load the CPSR along with the PC, or force transfer of user bank when in privileged mode.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR EXAMPLES LDMFD STMIA LDMFD LDMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ STMFD R13,{R0-R14}^ ; ; ; ; ; ; ; Unstack 3 registers. Save all registers. R15 ← (SP), CPSR unchanged. R15 ← (SP), CPSR <- SPSR_mode (allowed only in privileged modes). Save user mode regs on stack (allowed only in privileged modes).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP (SWP) 31 28 27 Cond 23 22 21 20 19 00010 B 00 16 15 Rn 12 11 Rd 8 7 0000 4 3 1001 0 Rm [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the Data Abort trap will be taken.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. 31 28 27 Cond 24 23 1111 0 Comment Field (Ignored by Processor) [31:28] Condition Field Figure 3-24. Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI{cond} {cond} Two character condition mnemonic, Table 3-2. Evaluated and placed in the comment field (which is ignored by ARM920T). Examples SWI SWI SWINE ReadC WriteI+"k” 0 ; Get next character from read stream. ; Output a "k" to the write stream. ; Conditionally call supervisor with 0 in comment field.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM920T, and it will not wait for the operation to complete.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). Assembler syntax CDP{cond} p#,,cd,cn,cm{,} {cond} Two character condition mnemonic. See Table 3-2.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX {cond}{L} p#,cd, LDC Load from memory to coprocessor STC Store from coprocessor to memory {L} When present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} Two character condition mnemonic. See Table 3-2..
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the PC+12.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 28 27 Cond 25 24 011 5 4 3 xxxxxxxxxxxxxxxxxxxx 1 0 xxxx Figure 3-28. Undefined Instruction If the condition is true, the undefined instruction trap will be taken.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP BEQ CMP BEQ Rn,#p Label Rm,#q Label ; If Rn=p OR Rm=q THEN GOTO Label.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers 6.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2 Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n 2.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE Rb,Ra,#3 Rb,{Rd,Rc} Rb,Ra,#3 Rb,Rb,LSL#3 Rd,Rd,LSR Rb Rb,Rb,#32 Rd,Rd,Rc,LSL Rb ; ; ; ; ; ; ; ; ; Enter with address in Ra (32 bits) uses Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Get word aligned address Get 64 bits containing answer Correction factor in bytes ...
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR NOTES 3-64
S3C2440A RISC MICROPROCESSOR 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions.Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 4-1.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Table 4-1.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 1: MOVE SHIFTED REGISTER 15 14 13 0 0 0 11 12 10 6 Offset5 Op 3 5 Rs 2 0 Rd [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 4-2. NOTE All instructions in this group set the CPSR condition codes. Table 4-2.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 4-6 ; Logical shift right the contents of R5 by 27 and store the result in R2.Set condition codes on the result.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 2: ADD/SUBTRACT 15 14 13 12 11 10 9 8 0 0 0 1 1 1 Op 6 5 3 2 Rs Rn/Offset3 0 Rd [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 4-3. Format 2 OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SUB 4-8 R0, R3, R4 R6, R2, #6 ; R0 := R3 + R4 and set condition codes on the result. ; R6 := R2 - 6 and set condition codes.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 14 13 0 0 0 12 11 Op 10 8 7 Rd 0 Offset8 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 4-4. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 4-4. NOTE All instructions in this group set the CPSR condition codes.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 4: ALU OPERATIONS 15 14 13 12 11 10 0 0 0 0 0 0 9 6 3 5 Op 2 0 Rd Rs [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes. Table 4-5.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 14 13 12 11 10 0 0 0 0 0 0 9 8 Op 7 6 H1 H2 3 5 2 0 Rd/Hd Rs/Hs [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 4-6. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assembler ARM equivalent Description 01 1 1 CMP Hd, Hs CMP Hd, Hs Compare two registers in the range 8-15. Set the condition code flags on the result. 10 0 1 MOV Rd, Hs MOV Rd, Hs Move a value from a register in the range 8-15 to a register in the range 07. 10 1 0 MOV Hd, Rs MOV Hd, Rs Move a value from a register in the range 0-7 to a register in the range 8-15.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET EXAMPLES Hi-Register Operations ADD CMP MOV PC, R5 R4, R12 R15, R14 ; PC := PC + R5 but don't set the condition codes. ; Set the condition codes on the result of R4 - R12. ; Move R14 (LR) into R15 (PC) but don't set the condition codes, eg. return from subroutine. Branch and Exchange ADR MOV BX R1,outofTHUMB R11,R1 R11 ALIGN CODE32 outofTHUMB ; Switch from THUMB to ARM state. ; Load address of outofTHUMB into R1.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 6: PC-RELATIVE LOAD 15 14 13 12 11 0 0 0 0 0 8 10 7 0 Word 8 Rd [7:0] Immediate Value [10:8] Destination Register Figure 4-7. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 4-7.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; Load into R3 the word found at the address formed by adding 844 to PC.bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 211 as the Word8 value.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 7: LOAD/STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 0 1 0 1 L B 0 8 6 Ro [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-8.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are preindexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8. Summary of Format 7 Instructions 1 L B 0 0 STR Rd, [Rb, Ro] STR Rd, [Rb, Ro] Pre-indexed word store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD 15 14 13 12 11 10 9 0 1 0 1 H S 1 8 6 3 5 2 Rb Ro 0 Rd [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 4-9. Format 8 OPERATION These instructions load optionally sign-extended bytes or halfwords, and store halfwords. The THUMB assembler syntax is shown below.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R4, [R3, R0] ; Store the lower 16 bits of R4 at the address formed by adding R0 to R3. LDSB R2, [R7, R1] ; Load into R2 the sign extended byte found at the address formed by adding R1 to R7.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET 15 14 13 12 11 0 1 1 B L 10 6 Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 4-10.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10. Table 4-10. Summary of Format 9 Instructions L B THUMB assembler ARM equivalent Description 0 0 STR Rd, [Rb, #Imm] STR Rd, [Rb, #Imm] Calculate the target address by adding together the value in Rb and Imm. Store the contents of Rd at the address.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 10: LOAD/STORE HALFWORD 15 14 13 12 11 0 1 0 0 L 10 6 3 5 Rb Offset5 2 0 Rd [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-11. Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] ; Store the lower 16 bits of R4 at the address formed by adding 56 R1. Note that the THUMB opcode will contain 28 as the Offset5 value.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 11: SP-RELATIVE LOAD/STORE 15 14 13 12 11 1 0 0 1 L 10 8 7 0 Word 8 Rd [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table. Table 4-12.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; Store the contents of R4 at the address formed by adding 492 to SP (R13).Note that the THUMB opcode will contain 123 as the Word8 value.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 12: LOAD ADDRESS 15 14 13 12 11 1 0 1 0 SP 10 8 7 0 Word 8 Rd [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 4-13. Format 12 OPERATION These instructions calculate an address by adding a 10-bit constant to either the PC or the SP, and load the resulting address into a register. The THUMB assembler syntax is shown in the following table. Table 4-13.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ; R2 := PC + 572, but don't set thecondition codes. bit[1] of PC is forced to zero.Note that the THUMB opcode willcontain 143 as the Word8 value.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 13: ADD OFFSET TO STACK POINTER 15 14 13 12 11 10 9 8 7 1 0 1 1 0 0 0 0 S 0 6 SWord 7 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax. Table 4-14.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 14: PUSH/POP REGISTERS 15 14 13 12 11 10 9 8 1 0 1 1 L 1 0 R 0 7 Rlist [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-15. Format 14 OPERATION The instructions in this group allow registers 0-7 and optionally LR to be pushed onto the stack, and registers 0-7 and optionally PC to be popped off the stack.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES 4-32 PUSH {R0-R4,LR} ; Store R0,R1,R2,R3,R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 15: MULTIPLE LOAD/STORE 15 14 13 12 11 1 1 0 0 L 10 8 0 7 Rlist Rb [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 4-16.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 16: CONDITIONAL BRANCH 15 14 13 12 1 1 0 1 11 8 7 0 SOffset 8 Cond [7:0] 8-bit Signed Immediate [11:8] Condition Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET Table 4-17.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 17: SOFTWARE INTERRUPT 15 14 13 12 11 10 9 8 1 1 0 1 1 1 1 1 7 0 Value 8 [7:0] Comment Field Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below. Table 4-18.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 18: UNCONDITIONAL BRANCH 15 14 13 12 11 1 1 1 0 0 10 0 Offset11 [10:0] Immediate Value Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. Table 4-19.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 19: LONG BRANCH WITH LINK 15 14 13 12 11 1 1 1 1 H 10 0 Offset [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 4-20. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 4-20.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following instructions are the code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = - 1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = - 1 SUB R1, R2 MOV pc, lr ARM Code signed_divide ANDS RSBMI EORS ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 RSBCS ; Effectively zero a4 as top bit will be shifted out later a4, a1, #&80000000 a1, a1, #0 ip, a4, a2,
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR NOTES 4-44
S3C2440A RISC MICROPROCESSOR 5 MEMORY CONTROLLER MEMORY CONTROLLER OVERVIEW The S3C2440A memory controller provides memory control signals that are required for external memory access. The S3C2440A has the following features: — Little/Big endian (selectable by a software) — Address space: 128Mbytes per bank (total 1GB/8 banks) — Programmable access size (8/16/32-bit) for all banks except bank0 (16/32-bit) — Total 8 memory banks Six memory banks for ROM, SRAM, etc.
MEMORY CONTROLLER 0x40000_0000 S3C2440A RISC MICROPROCESSOR OM[1:0] = 01,10 OM[1:0] = 00 SROM/SDRAM (nGCS7) SROM/SDRAM (nGCS7) 2MB/4MB/8MB/16MB /32MB/64MB/128MB Refer to Table 5-1 SROM/SDRAM (nGCS6) SROM/SDRAM (nGCS6) 2MB/4MB/8MB/16MB /32MB/64MB/128MB SROM (nGCS5) SROM (nGCS5) 128MB SROM (nGCS4) SROM (nGCS4) 128MB SROM (nGCS3) SROM (nGCS3) 128MB SROM (nGCS2) SROM (nGCS2) 128MB SROM (nGCS1) SROM (nGCS1) 128MB } 0x3800_0000 0x3000_0000 0x2800_0000 0x2000_0000 1GB HADDR[29:0] Acc
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 FUNCTION DESCRIPTION BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured with a width as one of 16-bit and 32-bit ones. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5-2.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 nWAIT PIN OPERATION If the WAIT bit(WSn bit in BWSCON) corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be de-asserted at the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE. HCLK ADDR nGCS nOE Tacs Tacc=4 Delayed Tcos Sampling nWAIT nWAIT DATA(R) Figure 5-2.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2440A will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. After nXBREQ is de-asserted, the nXBACK will also be de-asserted. HCLK SCLK SCKE, A[24:0] D[31:0], nGCS nOE,nWE nWBE nXBREQ 1clk nXBACK Figure 5-3.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 ROM Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nCE nWE nOE nGCSn Figure 5-4.
MEMORY CONTROLLER A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE S3C2440A RISC MICROPROCESSOR D0 D1 D2 D3 D4 D5 D6 D7 A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE0 A11 nOE A12 nGCSn A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D8 D9 D10 D11 D12 D13 D14 D15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE1 A11 nOE A12 nGCSn A13 A14 A15 A16 A17 nWE nOE nCE A0
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 SRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0 Figure 5-8.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR SDRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A21 A22 DQM0 DQM1 BA0 BA1 LDQM UDQM SCKE SCLK SCKE SCLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS nSRAS nSCAS nWE nSCS0 nSRAS nSCAS nWE Figure 5-10.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 PROGRAMMABLE ACCESS CYCLE HCLK A[24:0] nGCS Tacs Tcah Tcos Tacc Tacp nOE Tcoh nWE nWBE D[31:0](R) D[31:0] (W) Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR MCLK SCKE nSCS Trp nSRAS nSCAS Trcd ADDR BA BA A10/AP RA Ca Cb Cc Cd Ce BA BA BA BA BA BA Db Dc Dd De Db Dc Dd RA DATA (CL2) Da DATA (CL3) Da De nWE DQM Bank Precharge Row Active Write Trp = 2 cycle Trcd = 2 cycle Read (CL = 2, CL = 3, BL = 1) Tcas = 2 cycle Tcp = 2 cycle Figure 5-13.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register Address R/W Description Reset Value BWSCON 0x48000000 R/W Bus width & wait status control register 0x000000 BWSCON Bit Description ST7 [31] Determines SRAM for using UB/LB for bank 7. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) 0 WS7 [30] Determines WAIT status for bank 7.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) WS2 [10] Determines WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable DW2 [9:8] Determines data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 0 11 = reserved ST1 [7] Determines SRAM for using UB/LB for bank 1. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) 0 WS1 [6] Determines WAIT status for bank 1.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register Address R/W Description Reset Value BANKCON6 0x4800001C R/W Bank 6 control register 0x18008 BANKCON7 0x48000020 R/W Bank 7 control register 0x18008 BANKCONn MT Bit [16:15] Description Initial State Determine the memory type for bank6 and bank7. 00 = ROM or SRAM 01 = Reserved (Do not use) 10 = Reserved (Do not use) 11 = Sync.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 REFRESH CONTROL REGISTER Register Address R/W Description Reset Value REFRESH 0x48000024 R/W SDRAM refresh control register 0xac0000 REFRESH REFEN TREFMD Trp Bit [23] [22] [21:20] Description SDRAM Refresh Enable 0 = Disable Initial State 1 1 = Enable (self or CBR/auto refresh) SDRAM Refresh Mode 0 = CBR/Auto Refresh 1 = Self Refresh In self-refresh time, the SDRAM control signals are driven to the appropriate level.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BANKSIZE REGISTER Register Address R/W Description Reset Value BANKSIZE 0x48000028 R/W Flexible bank size register 0x0 BANKSIZE BURST_EN Bit [7] Description ARM core burst operation enable. Initial State 0 0 = Disable burst operation. 1 = Enable burst operation.
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR NOTES 5-20
S3C2440A RISC MICROPROCESSOR 6 NAND FLASH CONTROLLER NAND FLASH CONTORLLER OVERVIEW In recent times, NOR flash memory gets high in price while an SDRAM and a NAND flash memory is comparatively economical , motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM. S3C2440A boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C2440A is equipped with an internal SRAM buffer called ‘Steppingstone’.
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR BLOCK DIAGRAM ljjGnU uhukGmshzo p SYSTEM BUS zmy jGM zGt hoi zGpVm zGz j nFCE CLE ALE nFRE nFWE FRnB I/O0 - I/O15 zGz O[riGzyhtP Figure 6-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION REGISTERS AUTO BOOT CORE ACCESS (Boot Code) zGz O[riGiP uhukGmshzo j USER ACCESS uhukGmshzo t zGm y Figure 6-2 NAND Flash Controller Boo
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER PIN CONFIGURATION OM[1:0] = 00: Enable NAND flash memory boot NCON : NAND flash memory selection(Normal / Advance) 0: Normal NAND flash(256Words/512Bytes page size, 3/4 address cycle) 1: Advance NAND flash(1KWords/2KBytes page size, 4/5 address cycle) GPG13 : NAND flash memory page capacitance selection 0: Page=256Words(NCON = 0) or Page=1KWords(NCON = 1) 1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1) GPG14: NAND flash memory address
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR NAND FLASH MEMORY TIMING TACLS TWRPH0 TWRPH1 HCLK CLE / ALE nWE COMMAND / ADDRESS DATA Figure 6-3.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER SOFTWARE MODE S3C2440A supports only software mode access. Using this mode, you can completely access the NAND flash memory. The NAND Flash Controller supports direct access interface with the NAND flash memory.
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR Data Register Configuration 1) 16-bit NAND Flash Memory Interface A. Word Access Register NFDATA NFDATA B.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC(Error Correction Code) NAND Flash controller consists of four ECC (Error Correction Code) modules. The two ECC modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ECC Parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ECC Parity code generation.
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR ECC MODULE FEATURES ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH MEMORY MAPPING 0xFFFF_FFFF Not Used Not Used SFR Area SFR Area BootSRAM (4KB) Not Used 0x6000_0000 0x4800_0000 0x4000_0FFF 0x4000_0000 0x3800_0000 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x0000_0000 SDRAM SDRAM (BANK7, nGCS7) (BANK7, nGCS7) SDRAM (BANK6, nGCS6) SDRAM (BANK6, nGCS6) SROM (BANK5, nGCS5) SROM (BANK5, nGCS5) SROM (BANK4, nGCS4) SROM (BANK4, nGCS4) SROM (BANK3, nGCS3) SROM (
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR NAND FLASH MEMORY CONFIGURATION RnB nFRE R/ B I/O7 DATA[7] RE I/O6 DATA[6] nFCE CE I/O5 DATA[5] CLE CLE I/O4 DATA[4] ALE nFWE ALE I/O3 DATA[3] WE I/O2 DATA[2] I/O1 DATA[1] I/O0 DATA[0] Figure 6-1 A 8-bit NAND Flash Memory Interface When you write the address, the same address is issued from data[7:0] and data[15:8] Rn B R/ B I/O7 DATA[7] Rn B R/ B I/O7 DATA[15] nFRE RE I/O6 DATA[6] nFRE RE I/O6 DATA[14] nFCE CE
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER Nand Flash configuration Register Register Address R/W Description Reset Value NFCONF 0x4E000000 R/W NAND Flash Configuration register 0x0000100X Description Initial State NFCONF Bit Reserved [15:14] Reserved TACLS [13:12] CLE & ALE duration setting value (0~3) 01 Duration = HCLK x TACLS Reserved [11] TWRPH0 [10:8] Reserved TWRPH0 duration setting value (0~7) 0 000 Duration = HCLK x ( TWRPH0 + 1 ) Reserved [7] TWRPH1 [6:4] R
NAND FLASH CONTROLLER AdvFlash (Read only) S3C2440A RISC MICROPROCESSOR [3] Advance NAND flash memory for auto-booting H/W Set 0: Support 256 or 512 byte/page NAND flash memory (NCON0) 1: Support 1024 or 2048 byte/page NAND flash memory This bit is determined by NCON0 pin status during reset and wake-up from sleep mode.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER CONTROL REGISTER Register Address R/W NFCONT 0x4E000004 R/W NFCONT Description NAND Flash control register Bit Reserved [14:15] Lock-tight [13] Reset Value 0x0384 Description Initial State Reserved 0 Lock-tight configuration 0 0: Disable lock-tight 1: Enable lock-tight, Once this bit is set to 1, you cannot clear. Only reset or wake up from sleep mode can make this bit disable(can not cleared by software).
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 0: Unlock Spare ECC 1: Lock Spare ECC Spare area ECC status register is NFSECC(0x4E000034), MainECCLock [5] Lock Main data area ECC generation 1 0: Unlock Main data area ECC generation 1: Lock Main data area ECC generation Main area ECC status register is NFMECC0/1(0x4E00002C/30), InitECC [4] Initialize ECC decoder/encoder(Write-only) 0 1: Initialize ECC decoder/encoder Reserved [2:3] Reg_nCE [1] Reserved 00 NAND Flash Memory nFCE signal
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER COMMAND REGISTER Register Address R/W NFCMMD 0x4E000008 R/W NFCMMD Description NAND Flash command set register Bit Description Reset Value 0x00 Initial State Reserved [15:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 ADDRESS REGISTER Register Address R/W NFADDR 0x4E00000C R/W Description NAND Flash address set register Description Reset Value 0x0000XX00 REG_ADDR Bit Initial State Reserved [15:8] Reserve
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR MAIN DATA AREA REGISTER Register Address R/W NFMECCD0 0x4E000014 R/W Description st nd NAND Flash ECC 1 and 2 register for main data read Reset Value 0x00000000 Note: Refer to ECC MODULE FEATURES in Page 6-8. NFMECCD1 0x4E000018 R/W rd th NAND Flash ECC 3 4 register for main data read 0x00000000 Note: Refer to ECC MODULE FEATURES in Page 6-8.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER SPARE AREA ECC REGISTER Register Address NFSECCD 0x4E00001C NFSECCD ECCData1_1 ECCData1_0 R/W Description R/W NAND Flash ECC(Error Correction Code) register for spare 0x00000000 area data read Bit [31:24] [23:16] Reset Value Description Initial State nd 0x00 nd 0x00 2 ECC for I/O[15:8] 2 ECC for I/O[ 7:0] Note: In Software mode, Read this register when you need to nd read 2 ECC value from NAND flash memory.
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR NFCON STATUS REGISTER Register NFSTAT Address R/W Description 0x4E000020 R/W NAND Flash operation status register NFSTAT Bit Description Reset Value 0xXX00 Initial State Reserved [7] Reserved X Reserved [4:6] Reserved 0 IllegalAccess [3] Once Soft Lock or Lock-tight is enabled, The illegal access (program, erase) to the memory makes this bit set.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC0/1 STATUS REGISTER Register Address NFESTAT0 0x4E000024 R/W NAND Flash ECC Status register for I/O [7:0] 0x00000000 NFESTAT1 0x4E000028 R/W NAND Flash ECC Status register for I/O [15:8] 0x00000000 NFESTAT0 R/W Bit Description Description Reset Value Initial State SErrorDataNo [24:21] In spare area, Indicates which number data is error 00 SErrorBitNo [20:18] In spare area, Indicates which bit is error 000 MErrorDataNo [17:7]
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR MAIN DATA AREA ECC0 STATUS REGISTER Register Address R/W Description Reset Value NFMECC0 0x4E00002C R NAND Flash ECC register for data[7:0] 0xXXXXXX NFMECC1 0x4E000030 R NAND Flash ECC register for data[15:8] 0xXXXXXX NFMECC0 Bit Description Initial State MECC0_3 [31:24] ECC3 for data[7:0] 0xXX MECC0_2 [23:16] ECC2 for data[7:0] 0xXX MECC0_1 [15:8] ECC1 for data[7:0] 0xXX MECC0_0 [7:0] ECC0 for data[7:0] 0xXX NFMECC1 Bit
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER BLOCK ADDRESS REGISTER Register Address R/W Description Reset Value NFSBLK 0x4E000038 R/W NAND Flash programmable start block address 0x000000 NFEBLK 0x4E00003C R/W NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address. When the Soft lock or Lock-tight is enabled and the Start and End address has same value, Entire area of NAND flash will be locked.
NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[12]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[13]) is set.
S3C2440A RISC MICROPROCESSOR 7 CLOCK & POWER MANAGEMENT CLOCK & POWER MANAGEMENT OVERVIEW The Clock & Power management block consists of three parts: Clock control, USB control, and Power control. The Clock control logic in S3C2440A can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2440A has two Phase Locked Loops (PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz).
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop), which generate the high frequency clock required in the S3C2440A.
S3C2440A RISC MICROPROCESSOR P[5:0] M[7:0] S[1:0] OM[3:2] XTIpll XTOpll OSC CLOCK & POWER MANAGEMENT MPLLin MPLL EXTCLK MPLLin CLK UPLL CLK HCLK PCLK RTC XTAL CLK CLKCNTL Mpll FCLK HDIVN Control Signal PDIVN CLKOUT F H P POWCNTL USBCNTL DIVN_UPLL 1/1 or 1/2 Upll P[5:0] M[7:0] S[1:0] UPLL Power Management Block Test mode OM[1:0] UCLK HCLK ARM920T FCLK PCLK Nand Flash Controller H_USB H_Nand USB Host I/F H_CAM CAMDIVN CAM TIC ExtMater Memory Controller Interrupt Controller B
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase.
S3C2440A RISC MICROPROCESSOR Divider P Fin CLOCK & POWER MANAGEMENT Loop Filter Fref PFD PUMP R C P[5:0] Fvco M[7:0] CLF Divider M VCO Internal External Divider S S[1:0] MPLLCAP, UPLLCAP MPLL,UPLL Figure 7-2. PLL (Phase-Locked Loop) Block Diagram VDD EXTCLK External OSC EXTCLK VDD CEXT XTIpll XTIpll XTOpll XTOpll CEXT a) X-TAL Oscillation (OM[3:2]=00) b) External Clock Source (OM[3:2]=11) Figure 7-3.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK CONTROL LOGIC The Clock Control Logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Change PLL Settings In Normal Operation Mode During the operation of the S3C2440A in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the internal blocks in the S3C2440A. Figure 7-5 shows the timing diagram. Mpll PMS setting PLL Lock-time FCLK It changes to new PLL clock after automatic lock time. Figure 7-5.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI. The S3C2440A supports selection of Dividing Ratio between FCLK, HLCK and PCLK.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT NOTE 1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK. 2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions(S3C2440 does not support synchronous bus mode). MMU_SetAsyncBusMode mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR POWER MANAGEMENT The Power Management block controls the system clocks by software for the reduction of power consumption in the S3C2440A. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals. Figure 7-7 shows the clock distribution of the S3C2440A. The S3C2440A has four power modes. The following section describes each power management mode. The transition between the modes is not allowed freely.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT IDLE_BIT=1 IDLE Interrupts, EINT[0:23], RTC alarm RESET NORMAL (SLOW_BIT=0) EINT[15:0], RTC alarm SLOW (SLOW_BIT=1) SLEEP BIT=1 SLEEP Figure 7-8. Power Management State Diagram Table 7-2. Clock and Power State in Each Power Mode Mode ARM920T Power AHB Modules (1) Management /WDT GPIO 32.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR NORMAL Mode In Normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate completely. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode. Figure 7-11(Please check the figure correctly) shows the timing diagram. Mpll SLOW_BIT Slow mode enable Slow mode disable Divided external clock It changes to PLL clock after slow mode off MPLL_OFF FCLK Figure 7-9.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13 (Please check for the figure number correctly) shows the timing diagram.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT SLEEP Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR Follow the Procedure to Wake-up from SLEEP mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. It’s exactly same with the case of the assertion of the external nRESET pin. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency). 2.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Power Control of VDDi and VDDiarm In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDUPLL will be turned off, which is controlled by PWREN pin. If PWREN signal is activated(H), VDDi and VDDiarm are supplied by an external voltage regulator. If PWREN pin is inactive (L), the VDDi and VDDiarm are turned off. NOTE Although VDDi, VDDiarm, VDDMPLL and VDDUPLL may be turned off, the other power pins have to be supplied. Regulator 1.2V/1.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR Signaling EINT[15:0] for Wakeup The S3C2440A can be woken up from SLEEP mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising, falling or both) are asserted on EINTn input pin. b) The EINTn pin has to be configured as EINT in the GPIO control register. c) nBATT_FLT pin has to be H level.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Output Port State and SLEEP Mode The output port should have a proper logic level in power off mode, which makes the current consumption minimized. If there is no load on an output port pin, H level is preferred. If output is L, the current will be consumed through the internal parasitic resistance; if the output is H, the current will not be consumed. For an output port, the current consumption can be reduced if the output state is H.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register Address R/W Description Reset Value LOCKTIME 0x4C000000 R/W PLL lock time count register 0xFFFFFFFF LOCKTIME Bit Description Initial State U_LTIME [31:16] UPLL lock time count value for UCLK.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT PLL CONTROL REGISTER (MPLLCON & UPLLCON) Register Address R/W Description Reset Value MPLLCON 0x4C000004 R/W MPLL configuration register 0x00096030 UPLLCON 0x4C000008 R/W UPLL configuration register 0x0004d030 PLLCON Bit Description Initial State MDIV [19:12] Main divider control 0x96 / 0x4d PDIV [9:4] Pre-divider control 0x03 / 0x03 SDIV [1:0] Post divider control 0x0 / 0x0 NOTE When you set MPLL&UPLL values, you have t
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK CONTROL REGISTER (CLKCON) Register Address R/W Description Reset Value CLKCON 0x4C00000C R/W Clock generator control register 0xFFFFF0 CLKCON AC97 Bit [20] Camera [19] SPI [18] IIS [17] IIC [16] ADC(&Touch Screen) [15] RTC [14] GPIO [13] UART2 [12] UART1 [11] UART0 [10] SDI [9] PWMTIMER [8] USB device [7] USB host [6] LCDC [5] NAND Flash Controller [4] SLEEP [3] IDLE BIT [2] Reserved [1:0] 7-22 D
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Description Reset Value CLKSLOW 0x4C000010 R/W Slow clock control register 0x00000004 CLKSLOW UCLK_ON Bit [7] Description 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) Initial State 0 1: UCLK OFF (UPLL is also turned off.) Reserved [6] Reserved – MPLL_OFF [5] 0: Turn on PLL.
CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address R/W Description Reset Value CLKDIVN 0x4C000014 R/W Clock divider control register 0x00000000 CLKDIVN Bit DIVN_UPLL [3] Description UCLK select register(UCLK must be 48MHz for USB) Initial State 0 0: UCLK = UPLL clock 1: UCLK = UPLL clock / 2 Set to 0, when UPLL clock is set as 48Mhz Set to 1. when UPLL clock is set as 96Mhz. HDIVN [2:1] 00 : HCLK = FCLK/1.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER Register Address R/W Description Reset Value CAMDIVN 0x4C000018 R/W Camera clock divider register 0x00000000 CAMDIVN DVS_EN Bit [12] Description 0:DVS OFF ARM core will run normally with FCLK(MPLLout). Initial State 0 1:DVS ON ARM core will run at the same clock as system clock(HCLK). Reserved [11] 0 Reserved [10] 0 HCLK4_HALF [9] HDIVN division rate change bit, when CLKDIVN[2:1]=10b.
S3C2440A RISC MICROPROCESSOR 8 DMA DMA OVERVIEW The S3C2440A supports four-channel DMA controller located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions.
DMA S3C2440A RISC MICROPROCESSOR DMA REQUEST SOURCES Each channel of the DMA controller can select one of the DMA request source among four DMA sources, if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) Table 8-1 shows four DMA sources for each channel. Table 8-1.
S3C2440A RISC MICROPROCESSOR DMA EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols. Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one DMA operation.
DMA S3C2440A RISC MICROPROCESSOR Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand mode - If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted.
S3C2440A RISC MICROPROCESSOR DMA Transfer Size - There are two different transfer sizes; unit and Burst 4. - DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus. Burst 4 Transfer Size There will be four sequential Reads and Writes performed in the Burst 4 Transfer respectively. Note Unit Transfer size: One read and one write is performed.
DMA S3C2440A RISC MICROPROCESSOR EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ will be a need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed. XSCLK XnXDREQ XnXDACK Double synch Read Write Read Write Figure 8-4.
S3C2440A RISC MICROPROCESSOR DMA DMA SPECIAL REGISTERS Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The details of those registers are as follows.
DMA S3C2440A RISC MICROPROCESSOR DMA INITIAL DESTINATION (DIDST) REGISTER Register Address R/W Description Reset Value DIDST0 0x4B000008 R/W DMA 0 initial destination register 0x00000000 DIDST1 0x4B000048 R/W DMA 1 initial destination register 0x00000000 DIDST2 0x4B000088 R/W DMA 2 initial destination register 0x00000000 DIDST3 0x4B0000B8 R/W DMA 3 initial destination register 0x00000000 DIDSTn D_ADDR Bit Description Initial State [30:0] Base address (start address) of destin
S3C2440A RISC MICROPROCESSOR DMA DMA CONTROL (DCON) REGISTER Register Address R/W Description Reset Value DCON0 0x4B000010 R/W DMA 0 control register 0x00000000 DCON1 0x4B000050 R/W DMA 1 control register 0x00000000 DCON2 0x4B000090 R/W DMA 2 control register 0x00000000 DCON3 0x4B0000D0 R/W DMA 3 control register 0x00000000 DCONn DMD_HS Bit [31] Description Select one between Demand mode and Handshake mode. Initial State 0 0: Demand mode will be selected.
DMA S3C2440A RISC MICROPROCESSOR DCONn Bit SERVMODE [27] Description Initial State Select the service mode between Single service mode and Whole service mode. 0 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request are not required.
S3C2440A RISC MICROPROCESSOR DMA DMA STATUS (DSTAT) REGISTER Register Address R/W Description Reset Value DSTAT0 0x4B000014 R DMA 0 count register 000000h DSTAT1 0x4B000054 R DMA 1 count register 000000h DSTAT2 0x4B000094 R DMA 2 count register 000000h DSTAT3 0x4B0000D4 R DMA 3 count register 000000h DSTATn STAT Bit [21:20] Description Status of this DMA controller. Initial State 00b 00: Indicates that DMA controller is ready for another DMA request.
DMA S3C2440A RISC MICROPROCESSOR DMA CURRENT SOURCE (DCSRC) REGISTER Register Address R/W Description Reset Value DCSRC0 0x4B000018 R DMA 0 current Source Register 0x00000000 DCSRC1 0x4B000058 R DMA 1 current Source Register 0x00000000 DCSRC2 0x4B000098 R DMA 2 current Source Register 0x00000000 DCSRC3 0x4B0000D8 R DMA 3 current Source Register 0x00000000 DCSRCn CURR_SRC Bit [30:0] Description Current source address for DMAn Initial State 0x00000000 CURRENT DESTINATION (DCDST)
S3C2440A RISC MICROPROCESSOR DMA DMA MASK TRIGGER (DMASKTRIG) REGISTER Register Address R/W Description Reset Value DMASKTRIG0 0x4B000020 R/W DMA 0 mask trigger register 000 DMASKTRIG1 0x4B000060 R/W DMA 1 mask trigger register 000 DMASKTRIG2 0x4B0000A0 R/W DMA 2 mask trigger register 000 DMASKTRIG3 0x4B0000E0 R/W DMA 3 mask trigger register 000 DMASKTRIGn Bit STOP [2] Description Stop the DMA operation.
DMA S3C2440A RISC MICROPROCESSOR NOTES 8-14
S3C2440A RISC MICROPROCESSOR 9 I/O PORTS I/O PORTS OVERVIEW S3C2440A has 130 multi-functional input/output port pins and there are eight ports as shown below: - Port A(GPA): 25-output port - Port B(GPB): 11-input/out port - Port C(GPC): 16-input/output port - Port D(GPD): 16-input/output port - Port E(GPE): 16-input/output port - Port F(GPF): 8-input/output port - Port G(GPG): 16-input/output port - Port H(GPH): 9-input/output port - Port J(GPJ): 13-input/output port Each port can be easily configured b
I/O PORTS S3C2440A RISC MICROPROCESSOR Table 9-1.
S3C2440A RISC MICROPROCESSOR I/O PORTS Table 9-1.
I/O PORTS S3C2440A RISC MICROPROCESSOR Table 9-1.
S3C2440A RISC MICROPROCESSOR I/O PORTS Table 9-1.
I/O PORTS S3C2440A RISC MICROPROCESSOR Table 9-1.
S3C2440A RISC MICROPROCESSOR I/O PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPJCON) In S3C2440A, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins. The PnCON(port control register) determines which function is used for each pin. If PE0 – PE7 is used for the wakeup signal in power down mode, these ports must be configured in interrupt mode.
I/O PORTS S3C2440A RISC MICROPROCESSOR I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS(GPACON, GPADAT) 9-8 Register Address R/W Description GPACON 0x56000000 R/W Configures the pins of port A 0xffffff GPADAT 0x56000004 R/W The data register for port A Undef.
S3C2440A RISC MICROPROCESSOR GPADAT Bit GPA[24:0] [24:0] I/O PORTS Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
I/O PORTS S3C2440A RISC MICROPROCESSOR PORT B CONTROL REGISTERS(GPBCON, GPBDAT, GPBUP) Register Address R/W Description GPBCON 0x56000010 R/W Configures the pins of port B GPBDAT 0x56000014 R/W The data register for port B GPBUP 0x56000018 R/W pull-up disable register for port B Reserved 0x5600001c PBCON Bit GPB10 [21:20] 00 = Input 10 = nXDREQ0 01 = Output 11 = reserved GPB9 [19:18] 00 = Input 10 = nXDACK0 01 = Output 11 = reserved GPB8 [17:16] 00 = Input 10 = nXDREQ1 01 =
S3C2440A RISC MICROPROCESSOR I/O PORTS PORT C CONTROL REGISTERS(GPCCON, GPCDAT, GPCUP) Register Address R/W Description GPCCON 0x56000020 R/W Configures the pins of port C GPCDAT 0x56000024 R/W The data register for port C GPCUP 0x56000028 R/W pull-up disable register for port C Reserved 0x5600002c - - Reset Value 0x0 Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR GPCDAT Bit GPC[15:0] [15:0] GPCUP Bit GPC[15:0] [15:0] 9-12 Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
S3C2440A RISC MICROPROCESSOR I/O PORTS PORT D CONTROL REGISTERS(GPDCON, GPDDAT, GPDUP) Register Address R/W Description GPDCON 0x56000030 R/W Configures the pins of port D GPDDAT 0x56000034 R/W The data register for port D Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR GPDDAT Bit GPD[15:0] [15:0] GPDUP Bit GPD[15:0] [15:0] 9-14 Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
S3C2440A RISC MICROPROCESSOR I/O PORTS PORT E CONTROL REGISTERS(GPECON, GPEDAT, GPEUP) Register Address R/W Description GPECON 0x56000040 R/W Configures the pins of port E GPEDAT 0x56000044 R/W The data register for port E Undef. GPEUP 0x56000048 R/W pull-up disable register for port E 0x0000 Reserved 0x5600004c - GPECON Bit GPE15 [31:30] 00 = Input 01 = Output 10 = IICSDA 11 = Reserved This pad is open-drain, There is no Pull-up option.
I/O PORTS S3C2440A RISC MICROPROCESSOR . GPEDAT Bit Description GPE[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read. GPEUP Bit GPE[13:0] [13:0] 9-16 Description 0: the pull up function attached to to the corresponding port pin is enabled.
S3C2440A RISC MICROPROCESSOR I/O PORTS PORT F CONTROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register Address R/W Description GPFCON 0x56000050 R/W Configures the pins of port F GPFDAT 0x56000054 R/W The data register for port F Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR PORT G CONTROL REGISTERS(GPGCON, GPGDAT) If GPG0 - GPG7 will be used for wake-up signals at Sleep mode, the ports will be set in interrupt mode. Register Address R/W Description GPGCON 0x56000060 R/W Configures the pins of port G GPGDAT 0x56000064 R/W The data register for port G Undef.
S3C2440A RISC MICROPROCESSOR GPGDAT Bit GPG[15:0] [15:0] I/O PORTS Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. GPGUP Bit GPG[15:0] [15:0] Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
I/O PORTS S3C2440A RISC MICROPROCESSOR PORT H CONTROL REGISTERS(GPHCON, GPHDAT) 9-20 Register Address R/W Description GPHCON 0x56000070 R/W Configures the pins of port H GPHDAT 0x56000074 R/W The data register for port H Undef.
S3C2440A RISC MICROPROCESSOR GPHDAT Bit GPH[10:0] [10:0] I/O PORTS Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. GPHUP Bit GPH[10:0] [10:0] Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
I/O PORTS S3C2440A RISC MICROPROCESSOR PORT J CONTROL REGISTERS(GPJCON, GPJDAT) 9-22 Register Address R/W Description GPJCON 0x560000d0 R/W Configures the pins of port J GPJDAT 0x560000d4 R/W The data register for port J Undef.
S3C2440A RISC MICROPROCESSOR GPJDAT Bit GPJ15:0] [12:0] I/O PORTS Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. GPJUP Bit GPJ[12:0] [12:0] Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
I/O PORTS S3C2440A RISC MICROPROCESSOR MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the characteristics of IO pad, the data bus pull-up resisters have to be turned on or off to reduce the power consumption. D[31:0] pin pull-up resisters can be controlled by MISCCR register. Pads related USB are controlled by this register for USB host, or for USB device.
S3C2440A RISC MICROPROCESSOR (1) CLKSEL1 [10:8] I/O PORTS Select source clock with CLKOUT1 pad 000 000 = MPLL output 001 = UPLL output 010 = RTC clock output 011 = HCLK 100 = PCLK 101 = DCLK1 11x = reserved Reserved CLKSEL0 (1) [7] [6:4] Select source clock with CLKOUT0 pad 0 010 000 = MPLL INPUT Clock(XTAL) 001 = UPLL output 010 = FCLK 011 = HCLK 100 = PCLK 101 = DCLK0 11x = reserved SEL_USBPAD [3] USB1 Host/Device select register.
I/O PORTS S3C2440A RISC MICROPROCESSOR DCLK CONTROL REGISTERS(DCLKCON) Register Address R/W DCLKCON 0x56000084 R/W Description DCLK0/1 Control Register 0x0 DCLKCON Bit Description DCLK1CMP [27:24] DCLK1 Compare value clock toggle value.
S3C2440A RISC MICROPROCESSOR I/O PORTS EXTINTn(External Interrupt Control Register n) The 8 external interrupts can be requested by various signaling methods. The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter.
I/O PORTS EXTINT1 Bit FLTEN15 [31] EINT15 [30:28] FLTEN14 [27] EINT14 [26:24] FLTEN13 [23] EINT13 [22:20] FLTEN12 [19] EINT12 [18:16] FLTEN11 [15] EINT11 [14:12] FLTEN10 [11] EINT10 [10:8] FLTEN9 [7] EINT9 [6:4] FLTEN8 [3] EINT8 9-28 S3C2440A RISC MICROPROCESSOR [2:0] Description Filter Enable for EINT15 0 = Filter Disable 1= Filter Enable Setting the signaling method of the EINT15.
S3C2440A RISC MICROPROCESSOR EXTINT2 Bit FLTEN23 [31] EINT23 [30:28] FLTEN22 [27] EINT22 [26:24] I/O PORTS Description Filter Enable for EINT23 0 = Filter Disable EINT21 [23] [22:20] Filter Enable for EINT21 0 = Filter Disable FLTEN20 EINT20 [19] [18:16] Filter Enable for EINT20 0 = Filter Disable EINT19 [15] [14:12] Filter Enable for EINT19 0 = Filter Disable FLTEN18 EINT18 [11] [10:8] Filter Enable for EINT18 0 = Filter Disable [7] Filter Enable for EINT17 0 = Filter Disable 000
I/O PORTS EINT17 S3C2440A RISC MICROPROCESSOR [6:4] Setting the signaling method of the EINT17. 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered FLTEN16 EINT16 [3] [2:0] Filter Enable for EINT16 0 = Filter Disable 9-30 001 = High level 10x = Rising edge triggered 0 1= Filter Enable Setting the signaling method of the EINT16.
S3C2440A RISC MICROPROCESSOR I/O PORTS EINTFLTn(External Interrupt Filter Register n) To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter.
I/O PORTS S3C2440A RISC MICROPROCESSOR EINTMASK(External Interrupt Mask Register) Register Address R/W Description Reset Value EINTMASK 0x560000a4 R/W External interupt mask Register 0x000fffff EINTMASK Bit EINT23 [23] 0 = enable interrupt 1= masked EINT22 [22] 0 = enable interrupt 1= masked EINT21 [21] 0 = enable interrupt 1= masked EINT20 [20] 0 = enable interrupt 1= masked EINT19 [19] 0 = enable interrupt 1= masked EINT18 [18] 0 = enable interrupt 1= masked EINT17 [
S3C2440A RISC MICROPROCESSOR I/O PORTS EINTPEND(External Interrupt Pending Register) Register Address R/W Description Reset Value EINTPEND 0x560000a8 R/W External interupt pending Register 0x00 EINTPEND Bit EINT23 [23] It is cleard by writing “1” 0 = not occur 1= occur interrupt 0 EINT22 [22] It is cleard by writing “1” 0 = not occur 1= occur interrupt 0 EINT21 [21] It is cleard by writing “1” 0 = not occur 1= occur interrupt 0 EINT20 [20] It is cleard by writing “1” 0 = not occu
I/O PORTS 9-34 S3C2440A RISC MICROPROCESSOR EINT5 [5] It is cleard by writing “1” 0 = not occur 1= occur interrupt EINT4 [4] It is cleard by writing “1” 0 = not occur 1= occur interrupt Reserved [3:0] Reserved 0 0 0000
S3C2440A RISC MICROPROCESSOR I/O PORTS GSTATUSn (General Status Registers) Register Address R/W Description Reset Value GSTATUS0 0x560000ac R External pin status Not define GSTATUS1 0x560000b0 R/W Chip ID 0x32440001 GSTATUS2 0x560000b4 R/W Reset Status 0x1 GSTATUS3 0x560000b8 R/W Inform register 0x0 GSTATUS4 0x560000bc R/W Inform register 0x0 GSTATUS0 Bit nWAIT [3] Status of nWAIT pin NCON [2] Status of NCON pin RnB [1] Status of RnB pin BATT_FLT [0] Status of BA
I/O PORTS S3C2440A RISC MICROPROCESSOR DSCn (Drive Strength Control) Control the Memory I/O drive strength Register Address R/W Description Reset Value DSC0 0x560000c4 R/W strength control register 0 0x0 DSC1 0x560000c8 R/W strength control register 1 0x0 DSC0 Bit nEN_DSC [31] Reserved [30:10] DSC_ADR [9:8] DSC_DATA3 DSC_DATA2 DSC_DATA1 DSC_DATA0 9-36 [7:6] [5:4] [3:2] [1:0] Description Reset Value enable Drive Strength Control 0: enable 1: Disable 0 - 0 Address Bus Drive s
S3C2440A RISC MICROPROCESSOR DSC1 Bit DSC_SCK1 [29:28] DSC_SCK0 DSC_SCKE DSC_SDR [27:26] [25:24] [23:22] I/O PORTS Description Reset Value SCLK1 Drive strength. 00: 12mA 10: 10mA 01: 8mA 11: 6mA 00 SCLK0 Drive strength. 00: 12mA 10: 10mA 01: 8mA 11: 6mA SCKE Drive strength. 00: 10mA 10: 8mA 01: 6mA 11: 4mA nSRAS/nSCAS Drive strength. 00: 10mA 10: 8mA 01: 6mA 11: 4mA 00 00 00 DSC_NFC [21:20] Nand Flash Control Drive strength( nFCE, nFRE, nFWE, CLE, ALE).
I/O PORTS S3C2440A RISC MICROPROCESSOR MSLCON (Memory Sleep Control Register) Select memory interface status when in SLEEP mode. Register Address R/W Description Reset Value MSLCON 0x560000cc R/W Memory Sleep Control Register 0x0 MSLCON Bit PSC_DATA [11] DATA[31:0] pin status in Sleep mode. 0: Hi-Z 1: Output “0”. 0 PSC_WAIT [10] nWAIT pin status in Sleep mode. 0: Input 1: Output “0” 0 PSC_RnB [9] RnB pin status in Sleep mode.
S3C2440A RISC MICROPROCESSOR 10 PWM TIMER PWM TIMER OVERVIEW The S3C2440A has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device. The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler.
PWM TIMER S3C2440A RISC MICROPROCESSOR TCMPB0 1/2 8-Bit Prescaler 5:1 MUX PCLK TOUT0 Dead Zone Generator Control Logic0 Dead Zone 1/4 1/8 TCMPB1 TCNTB1 1/16 Clock Divider TOUT1 5:1 MUX TCLK0 TCMPB2 5:1 MUX 1/2 8-Bit Prescaler TCNTB0 Control Logic1 Dead Zone TCNTB2 Control Logic2 TOUT2 1/4 1/8 TCMPB3 TCNTB3 1/16 Clock Divider 5:1 MUX TCLK1 Control Logic3 TOUT3 TCNTB4 5:1 MUX Control Logic4 Figure 10-1.
S3C2440A RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings Minimum resolution (prescaler = 0) Maximum resolution (prescaler = 255) Maximum interval (TCNTBn = 65535) 1/2 (PCLK = 50 MHz) 0.0400 us (25.0000 MHz) 10.2400 us (97.6562 KHz) 0.6710 sec 1/4 (PCLK = 50 MHz) 0.0800 us (12.5000 MHz) 20.4800 us (48.8281 KHz) 1.3421 sec 1/8 (PCLK = 50 MHz) 0.1600 us ( 6.2500 MHz) 40.
PWM TIMER S3C2440A RISC MICROPROCESSOR AUTO RELOAD & DOUBLE BUFFERING S3C2440A PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into Timer Count Buffer register (TCNTBn) and the current counter value of the timer can be read from Timer Count Observation register (TCNTOn).
S3C2440A RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how to start a timer: 1) Write the initial value into TCNTBn and TCMPBn. 2) Set the manual update bit of the corresponding timer.
PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER OPERATION 1 2 3 4 6 7 9 10 TOUTn 50 110 40 5 40 20 60 8 11 Figure 10-4. Example of a Timer Operation The above Figure 10-4 shows the result of the following procedure: 1. Enable the auto re-load function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively.
S3C2440A RISC MICROPROCESSOR PWM TIMER PULSE WIDTH MODULATION (PWM) 60 Write TCMPBn = 60 50 40 Write TCMPBn = 40 Write TCMPBn = 50 30 30 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. Figure 10-5 shows a PWM value determined by TCMPBn. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value.
PWM TIMER S3C2440A RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit. And then, TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 (recommended). 2. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn ≤ TCMPn, the output level is high.
S3C2440A RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0.
PWM TIMER S3C2440A RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits (in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request.
S3C2440A RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address R/W TCFG0 0x51000000 R/W TCFG0 Bit Description Configures the two 8-bit prescalers Description Reset Value 0x00000000 Initial State Reserved [31:24] 0x00 Dead zone length [23:16] These 8 bits determine the dead zone length.
PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address R/W TCFG1 0x51000004 R/W TCFG1 Bit Description 5-MUX & DMA mode selecton register Description Reset Value 0x00000000 Initial State Reserved [31:24] DMA mode [23:20] Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved 0000 MUX 4 [19:16] Select MUX input for PWM Timer4.
S3C2440A RISC MICROPROCESSOR PWM TIMER TIMER CONTROL (TCON) REGISTER Register Address R/W TCON 0x51000008 R/W TCON Description Timer control register Bit Description Reset Value 0x00000000 Initial state 0 Timer 4 auto reload on/off [22] Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) Timer 4 manual update (note) [21] Determine the manual update for Timer 4.
PWM TIMER S3C2440A RISC MICROPROCESSOR TCON (Continued) TCON Reserved Bit Description Initial state [7:5] Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Timer 0 auto reload on/off [3] Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) 0 Timer 0 output inverter on/off [2] Determine the output inverter on/off for Timer 0.
S3C2440A RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address R/W TCNTB0 0x5100000C R/W Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 R/W Timer 0 compare buffer register 0x00000000 TCMPB0 Description Bit Timer 0 compare buffer register TCNTB0 [15:0] Description Set compare buffer value for Timer 0 Bit Timer 0 count buffer register [15:0] Description Set count buffer value for Timer 0 Reset Value Initial
PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address R/W Description Reset Value TCNTB1 0x51000018 R/W Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C R/W Timer 1 compare buffer register 0x00000000 TCMPB1 Bit Description Initial State Timer 1 compare buffer register [15:0] Set compare buffer value for Timer 1 0x00000000 TCNTB1 Bit Description Initial State Timer 1 count buffer register [15:0]
S3C2440A RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address R/W TCNTB2 0x51000024 R/W Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 R/W Timer 2 compare buffer register 0x00000000 Bit Description TCMPB2 Timer 2 compare buffer register TCNTB2 [15:0] Description Set compare buffer value for Timer 2 Bit Timer 2 count buffer register [15:0] Description Set count buffer value for Timer 2 Reset Value Initial
PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address R/W TCNTB3 0x51000030 R/W Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 R/W Timer 3 compare buffer register 0x00000000 Bit Description TCMPB3 Timer 3 compare buffer register TCNTB3 [15:0] Description Set compare buffer value for Timer 3 Bit Timer 3 count buffer register [15:0] Description Set count buffer value for Timer 3 Reset Value Initial
S3C2440A RISC MICROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address R/W TCNTB4 0x5100003C R/W TCNTB4 Description Timer 4 count buffer register Bit Timer 4 count buffer register [15:0] Description Set count buffer value for Timer 4 Reset Value 0x00000000 Initial State 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register Address R/W TCNTO4 0x51000040 R TCNTO4 Timer 4 observation register Bit [15:0] Description Timer 4 count observation register De
PWM TIMER S3C2440A RISC MICROPROCESSOR NOTES 10-20
S3C2440A RISC MICROPROCESSOR 11 UART UART OVERVIEW The S3C2440A Universal Asynchronous Receiver and Transmitter (UART) provide three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UART can support bit rates up to 115.2K bps using system clock.
UART S3C2440A RISC MICROPROCESSOR BLOCK DIAGRAM P e r ip h e r a l B U S T r a n s m it t e r T r a n s m it F IF O R e g is te r ( F IF O m o d e ) T r a n s m it B u ff e r R e g is te r ( 6 4 B y te ) T r a n s m it H o ld in g R e g is te r (N o n -F IF O m o d e ) T r a n s m it S h ifte r C o n tr o l U n it B u a d -ra te G e n e ra to r TXDn C lo c k S o u r c e ( P C L K , F C L K / n ,U E X T C L K ) R e c e iv e r R e c e iv e S h ifte r R e c e iv e B u f fe r R e g is t e r ( 6 4
S3C2440A RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infrared mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
UART S3C2440A RISC MICROPROCESSOR Auto Flow Control (AFC) The S3C2440A's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter.
S3C2440A RISC MICROPROCESSOR UART RS-232C interface If the user wants to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface.
UART S3C2440A RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out.
S3C2440A RISC MICROPROCESSOR UART Baud-rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2440A's internal system clock or UEXTCLK. In other words, dividend is selectable by setting Clock Selection of UCONn.
UART S3C2440A RISC MICROPROCESSOR Infrared (IR) Mode The S3C2440A UART block supports infrared (IR) transmission and reception, which can be selected by setting the Infrared-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode.
S3C2440A RISC MICROPROCESSOR UART SIO Frame Data Bits Start Bit 0 1 0 1 0 Stop Bit 0 1 1 0 1 Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Data Bits Start Bit 0 1 0 1 0 0 Bit Time Stop Bit 1 1 0 1 Pulse Width = 3/16 Bit Frame Figure 11-5. Infrared Transmit Mode Frame Timing Diagram IR Receive Frame Data Bits Start Bit 0 1 0 1 0 0 Stop Bit 1 1 0 1 Figure 11-6.
UART S3C2440A RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block.
S3C2440A RISC MICROPROCESSOR UART UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block.
UART Tx Interrupt Type S3C2440A RISC MICROPROCESSOR [9] Interrupt request type. 0 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Tx buffer is empty in NonFIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) Rx Interrupt Type [8] Interrupt request type.
S3C2440A RISC MICROPROCESSOR UART UART CONTROL REGISTER (Continued) Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. (UART Tx Enable/Disable) 00 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1) Receive Mode [1:0] Determine which function is currently able to read data from UART receive buffer register.
UART S3C2440A RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block.
S3C2440A RISC MICROPROCESSOR UART UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block.
UART S3C2440A RISC MICROPROCESSOR UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block.
S3C2440A RISC MICROPROCESSOR UART UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block.
UART S3C2440A RISC MICROPROCESSOR UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block.
S3C2440A RISC MICROPROCESSOR UART UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0, UMSTAT1 in the UART block.
UART S3C2440A RISC MICROPROCESSOR UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block. UTXHn has an 8-bit data for transmission data.
S3C2440A RISC MICROPROCESSOR UART UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block.
UART S3C2440A RISC MICROPROCESSOR NOTES 11-22
S3C2440A RISC MICROPROCESSOR 12 USB HOST USB HOST CONTROLLER OVERVIEW S3C2440A supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.
USB HOST S3C2440A RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS The S3C2440A USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detailed information.
S3C2440A RISC MICROPROCESSOR 13 USB DEVICE USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer. USB device controller supports: • Full speed USB device controller compatible with the USB specification version 1.
USB DEVICE S3C2440A RISC MICROPROCESSOR MC_ADDR[13:0] MC_DATA_IN[31:0] RT_VM_IN SIU MC_DATA_OUT[31:0] RT_VP_IN USB_CLK RXD RT_VP_OUT SYS_CLK MCU & DMA I/F SIE RT_VM_OUT RT_UX_OEN SYS_RESETN MC_WR WR_RDN MC_CSN GFI RT_UXSUSPEND MC_INTR DREQN[3:0] DACKN[3:0] FIFOs Figure 13-1.
S3C2440A RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian. All reserved bit is zero. Common indexed registers depend on INDEX register (INDEX_REG) (offset address: 0X178) value.
USB DEVICE S3C2440A RISC MICROPROCESSOR EP2_DMA_CON Endpoint2 DMA control register 0x218(L) / 0x21B(B) EP2_DMA_UNIT Endpoint2 DMA unit counter register 0x21C(L) / 0x21F(B) EP2_DMA_FIFO Endpoint2 DMA FIFO counter register 0x220(L) / 0x223(B) EP2_DMA_TTC_L Endpoint2 DMA transfer counter low-byte register 0x224(L) / 0x227(B) EP2_DMA_TTC_M Endpoint2 DMA transfer counter middle-byte register 0x228(L) / 0x22B(B) EP2_DMA_TTC_H Endpoint2 DMA transfer counter high-byte register 0x22C(L) / 0x22F(B)
S3C2440A RISC MICROPROCESSOR USB DEVICE FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token.
USB DEVICE S3C2440A RISC MICROPROCESSOR POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register Address R/W Description Reset Value PWR_REG 0x52000144(L) 0x52000147(B) R/W (byte) Power management register 0x00 PWR_ADDR Bit MCU USB Reserved [7:4] - - USB_RESET [3] R MCU_RESUME [2] SUSPEND_MODE SUSPEND_EN 13-6 Description Initial State - - SET Set by the USB if reset signaling is received from the host.
S3C2440A RISC MICROPROCESSOR USB DEVICE INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a ‘1’ (not ‘0’) to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary.
USB DEVICE S3C2440A RISC MICROPROCESSOR Register Address R/W USB_INT_REG 0x52000158(L) 0x5200015B(B) R/W (byte) Description Reset Value USB interrupt pending/clear register 0x00 USB_INT_REG Bit MCU USB RESET Interrupt [2] R /CLEAR SET Set by the USB when it receives reset signaling. 0 RESUME Interrupt [1] R /CLEAR SET Set by the USB when it receives resume signaling, while in Suspend mode.
S3C2440A RISC MICROPROCESSOR USB DEVICE INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled.
USB DEVICE S3C2440A RISC MICROPROCESSOR Register Address R/W USB_INT_EN_REG 0x520016C(L) 0x5200016F(B) R/W (byte) INT_MASK_REG Description Determine which interrupt is enabled 0x04 Bit MCU USB RESET_INT_EN [2] R/W R Reset interrupt enable bit 0 = Interrupt disable 1 = Enable 1 Reserved [1] - - - 0 SUSPEND_INT_EN [0] R/W R Suspend interrupt enable bit 0 = Interrupt disable 1 = Enable 0 13-10 Description Reset Value Initial State
S3C2440A RISC MICROPROCESSOR USB DEVICE FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically.
USB DEVICE S3C2440A RISC MICROPROCESSOR INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register.
S3C2440A RISC MICROPROCESSOR USB DEVICE END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register.
USB DEVICE S3C2440A RISC MICROPROCESSOR END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address R/W Description Reset Value IN_CSR1_REG 0x52000184(L) 0x52000187(B) R/W (byte) IN END POINT control status register1 0x00 IN_CSR1_REG Bit MCU USB Reserved [7] - - CLR_DATA_ TOGGLE [6] R/W SENT_STALL [5] SEND_STALL FIFO_FLUSH Reserved IN_PKT_RDY 13-14 Description Initial State - - R/ CLEAR Used in Set-up procedure.
S3C2440A RISC MICROPROCESSOR USB DEVICE Register Address R/W Description Reset Value IN_CSR2_REG 0x52000188(L) 0x5200018B(B) R/W (byte) IN END POINT control status register2 0x20 IN_CSR2_REG Bit MCU USB Description Initial State AUTO_SET [7] R/W R If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core without any intervention from MCU. If the MCU writes less than MAXP data, IN_PKT_RDY bit has to be set by the MCU.
USB DEVICE S3C2440A RISC MICROPROCESSOR END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register Address R/W Description Reset Value OUT_CSR1_REG 0x52000190(L) 0x52000193(B) R/W (byte) End Point out control status register1 0x00 OUT_CSR1_REG Bit MCU USB Description CLR_DATA_TOGGLE [7] R/W CLEAR SENT_STALL [6] CLEAR /R SET SEND_STALL [5] R/W R FIFO_FLUSH [4] R/W CLEAR [3:1] [0] R/ CLEAR SET When the MCU writes a 1 to this bit, the data toggle sequence bit
S3C2440A RISC MICROPROCESSOR USB DEVICE Register Address R/W Description Reset Value OUT_CSR2_REG 0x52000194(L) 0x52000197(B) R/W (byte) End Point out control status register2 0x00 OUT_CSR2_REG Bit MCU USB Description Initial State AUTO_CLR [7] R/W R If the MCU is set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU. 0 ISO [6] R/W R Determine endpoint transfer type.
USB DEVICE S3C2440A RISC MICROPROCESSOR END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU.
S3C2440A RISC MICROPROCESSOR USB DEVICE DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register Address R/W Description Reset Value EP1_DMA_CON 0x52000200(L) 0x52000203(B) R/W (byte) EP1 DMA interface control register 0x00 EP2_DMA_CON 0x52000218(L) 0x5200021B(B) R/W (byte) EP2 DMA interface control register 0x00 EP3_DMA_CON 0x52000240(L) 0x52000243(B) R/W (byte) EP3 DMA interface control register 0x00 EP4_DMA_CON 0x52000258(L) 0x5200025B(B) R/W (byte) EP4 DMA interface control registe
USB DEVICE S3C2440A RISC MICROPROCESSOR DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode.
S3C2440A RISC MICROPROCESSOR USB DEVICE DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA mode, the MCU should set proper value by software.
USB DEVICE S3C2440A RISC MICROPROCESSOR DMA TOTAL TRANSFER COUNTER REGISTER (EPn_DMA_TTC_L,M,H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter).
S3C2440A RISC MICROPROCESSOR 14 INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S3C2440A receives the request from 60 interrupt sources. These interrupt sources are provided by internal peripherals such as DMA controller, UART, IIC, and others. In these interrupt sources, the UARTn, AC97 and EINTn interrupts are 'OR'ed to the interrupt controller.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller.
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 60 interrupt sources as shown in the table below.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT SUB SOURCES Sub Sources Source INT_AC97 AC97 interrupt INT_WDT_AC97 INT_WDT Watchdoc interrupt INT_WDT_AC97 INT_CAM_P P-port capture interrupt in camera interface INT_CAM INT_CAM_C C-port capture interrupt in camera interface INT_CAM INT_ADC_S ADC interrupt INT_ADC Touch screen interrupt (pen up/down) INT_ADC INT_TC 14-4 Descriptions INT_ERR2 UART2 error interrupt INT_UART2 INT_TXD2 UART2 transmit interrupt INT_UART2
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-1 below.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5.
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register.
INTERRUPT CONTROLLER 14-8 S3C2440A RISC MICROPROCESSOR SRCPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 = Requested 0 INT_SPI1 [29] 0 = Not requested, 1 = Requested 0 INT_UART0 [28] 0 = Not requested, 1 = Requested 0 INT_IIC [27] 0 = Not requested, 1 = Requested 0 INT_USBH [26] 0 = Not requested, 1 = Requested 0 INT_USBD [25] 0 = Not requested, 1 = Requested 0 INT_NFCON [24] 0 = Not requested,
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER . INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Please note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt).
INTERRUPT CONTROLLER 14-10 S3C2440A RISC MICROPROCESSOR INTMOD Bit Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ 0 INT_RTC [30] 0 = IRQ, 1 = FIQ 0 INT_SPI1 [29] 0 = IRQ, 1 = FIQ 0 INT_UART0 [28] 0 = IRQ, 1 = FIQ 0 INT_IIC [27] 0 = IRQ, 1 = FIQ 0 INT_USBH [26] 0 = IRQ, 1 = FIQ 0 INT_USBD [25] 0 = IRQ, 1 = FIQ 0 INT_NFCON [24] 0 = IRQ, 1 = FIQ 0 INT_URRT1 [23] 0 = IRQ, 1 = FIQ 0 INT_SPI0 [22] 0 = IRQ, 1 = FIQ 0 INT_SDI [21] 0 = IRQ, 1 = FIQ
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
INTERRUPT CONTROLLER 14-12 S3C2440A RISC MICROPROCESSOR INTMSK Bit Description Initial State INT_ADC [31] 0 = Service available, 1 = Masked 1 INT_RTC [30] 0 = Service available, 1 = Masked 1 INT_SPI1 [29] 0 = Service available, 1 = Masked 1 INT_UART0 [28] 0 = Service available, 1 = Masked 1 INT_IIC [27] 0 = Service available, 1 = Masked 1 INT_USBH [26] 0 = Service available, 1 = Masked 1 INT_USBD [25] 0 = Service available, 1 = Masked 1 INT_NFCON [24] 0 = Service
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY REGISTER (PRIORITY) Register Address PRIORITY 0x4A00000C R/W R/W Description IRQ priority control register Description Reset Value 0x7F PRIORITY Bit Initial State ARB_SEL6 [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 00 ARB_SEL5 [18:17] Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 00 ARB_SEL4
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER INTPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 = Requested 0 INT_SPI1 [29] 0 = Not requested, 1 = Requested 0 INT_UART0 [28] 0 = Not requested, 1 = Requested 0 INT_IIC [27] 0 = Not requested, 1 = Requested 0 INT_USBH [26] 0 = Not requested, 1 = Requested 0 INT_USBD [25] 0 = Not requested, 1 = Requested 0 INT_NFCON [24] 0 = Not requested, 1 = Re
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND.
S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register Address R/W SUBSRCPND 0X4A000018 R/W Description Indicate the interrupt request status.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
S3C2440A RISC MICROPROCESSOR 15 LCD CONTROLLER LCD CONTROLLER OVERVIEW The LCD controller in the S3C2440A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include: — Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) — The system memory is used as the display memory.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM System Bus TIMEGEN REGBANK LPC3600 LCC3600 LCDCDMA VIDPRCS VIDEO MUX VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAME / VSYNC / STV VM / VDEN / TP . . . LCD_LPCOE / LCD_LCCINV LCD_LPCREV / LCD_LCCREV LCD_LPCREVB / LCD_LCCREVB VD[23:0] LPC3600 is a timing control logic unit for LTS350Q1-PD1 or LTS350Q1-PD2. LCC3600 is a timing control logic unit for LTS350Q1-PE1 or LTS350Q1-PE2. Figure 15-1.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER Table 15-1. Relation between VCLK and CLKVAL (STN, HCLK=60MHz) CLKVAL 60MHz/X VCLK 2 60 MHz/4 15.0 MHz 3 60 MHz/6 10.0 MHz : : : 1023 60 MHz/2046 29.3 kHz VIDEO OPERATION The S3C2440A LCD controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 256 Level Color Mode Operation The S3C2440A LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display mode uses separate lookup tables for red, green, and blue.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER DITHERING AND FRAME RATE CONTROL In case of STN LCD display (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel. The main principle of gray and color level display on the STN panel based on FRC is described.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays. 4-bit Dual Scan Display Type A 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address 0000H 0004H Data A[31:0] B[31:0] • • • 1000H 1004H LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ...... L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ...... L[31:0] M[31:0] • • • LCD Panel Mono 4-bit Single Scan Display & 8-bit Single Scan Display: A[31] A[30] A[29] ...... A[0] B[31] B[30] ...... B[0] C[31] ...... C[0] ......
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 16 BPP Color mode 16 bits (5 bits of red, 6 bits of green, 5 bits of blue) of video data correspond to 1 pixel. But, stn controller will use only 12 bit color data. It means that only upper 4bit each color data will be used as pixel data ( R[15:12], G[10:7], B[4:1]).
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . . . . . . . . . . . . . 4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 8-bit Single Scan Display Figure 15-2.
S3C2440A RISC MICROPROCESSOR VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 . . . . . . VD2 G1 . . . . . . VD3 R1 LCD CONTROLLER 1 Pixel VD7 R1 VD6 G1 4-bit Dual Scan Display VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . VD3 R1 1 Pixel 4-bit Single Scan Display VD6 G1 VD5 B1 VD4 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . VD7 R1 1 Pixel 8-bit Single Scan Display Figure 15-3.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel. The VM signal provides an AC signal for the display.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER Full Frame Timing(MMODE = 0) INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1 Full Frame Timing(MMODE = 1, MVAL=0x2) INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1 INT_FrSyn First Line Timing VFRAME VM LINECNT decreases & Display the 1st line VLINE Display the last line of the previous frame LINECNT LINEBLANK VCLK WDLY WDLY First Line Check & Data Timing VFRAME VM VLINE WLH VCLK VD[7:0] WDLY Figure 15-4.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] D[23:0] 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 ... (BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] D[7:0] 000H P1 Dummy Bit 004H P2 Dummy Bit 008H P3 Dummy Bit ... P1 P2 P3 P4 ......
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H P2 P1 004H P4 P3 008H P6 P5 ... P1 P2 P3 P4 ......
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 D[15:8] D[7:0] ... (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 ... P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 ......
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 ...
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C2440A provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) x 16-bit SPSRAM. The palette supports 5:6:5 (R:G:B) format and 5:5:5:1(R:G:B:I) format. When the user uses 5:5:5:1 format, the intensity data(I) is used as a common LSB bit of each RGB data.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 1 2 R4 R2 R1 3 4 R3 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 5 R2 R1 R0 G4 G3 G2 G1 G0 A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] R4 A[6] B3 B2 B1 B0 I A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER INT_FrSyn VSYNC HSYNC VDEN VBPD+1 VSPW+1 LINEVAL +1 VFPD+1 1 Frame 1 Line HSYNC VCLK VD VDEN LEND HBPD+1 HSPW+1 HOZVAL+1 HFPD+1 Figure 15-6.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR SAMSUNG TFT LCD PANEL (3.5” PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD) The S3C2440A supports following SEC TFT LCD panels. 1. SAMSUNG 3.5” Portrait / 256K Color /Reflective a-Si TFT LCD. LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only 2. SAMSUNG 3.5” Portrait / 256K Color /Transflective a-Si TFT LCD.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY (TFT/STN) The S3C2440A supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-8), except the values of PAGEWIDTH and OFFSIZE. The video buffer in which the image is stored should be larger than the LCD panel screen in size. OFFSIZE PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD POWER ENABLE (STN/TFT) The S3C2440A provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled by the setting of ENVID automatically. The S3C2440A also supports INVPWREN bit to invert polarity of the PWREN signal.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address R/W LCDCON1 0X4D000000 R/W LCDCON1 Bit Description LCD control 1 register Description Reset Value 0x00000000 Initial State LINECNT (read only) [27:18] Provide the status of the line counter. Down count from LINEVAL to 0 0000000000 CLKVAL [17:8] Determine the rates of VCLK and CLKVAL[9:0].
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Control 2 Register Register Address R/W LCDCON2 0X4D000004 R/W LCDCON2 VBPD Description LCD control 2 register Reset Value 0x00000000 Bit Description Initial State [31:24] TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. 0x00 STN: These bits should be set to zero on STN LCD. LINEVAL [23:14] TFT/STN: These bits determine the vertical size of LCD panel.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER LCD Control 3 Register Register Address R/W LCDCON3 0X4D000008 R/W LCDCON3 HBPD (TFT) LCD control 3 register Reset Value 0x00000000 Bit Description Initial state [25:19] TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. 0000000 STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Control 4 Register Register Address R/W LCDCON4 0X4D00000C R/W LCDCON4 Bit Description LCD control 4 register Description Reset Value 0x00000000 Initial state MVAL [15:8] STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. 0X00 HSPW(TFT) [7:0] TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER LCD Control 5 Register Register Address R/W LCDCON5 0X4D000010 R/W LCDCON5 Bit Description LCD control 5 register Description Reset Value 0x00000000 Initial state Reserved [31:17] This bit is reserved and the value should be ‘0’. 0 VSTATUS [16:15] TFT: Vertical Status (read only). 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch 00 HSTATUS [14:13] TFT: Horizontal Status (read only).
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Control 5 Register (Continued) LCDCON5 Bit Description Initial state INVVDEN [6] TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted 0 INVPWREN [5] STN/TFT: This bit indicates the PWREN signal polarity. 0 = normal 1 = inverted 0 INVLEND [4] TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted 0 PWREN [3] STN/TFT: LCD_PWREN output signal enable/disable.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER FRAME BUFFER START ADDRESS 1 REGISTER Register Address R/W LCDSADDR1 0X4D000014 R/W LCDSADDR1 Description STN/TFT: Frame buffer start address 1 register Reset Value 0x00000000 Bit Description Initial State LCDBANK [29:21] These bits indicate A[30:22] of the bank location for the video buffer in the system memory. LCDBANK value cannot be changed even when moving the view port.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR FRAME Buffer Start Address 3 Register Register Address R/W LCDSADDR3 0X4D00001C R/W Description Reset Value STN/TFT: Virtual screen address set 0x00000000 Bit Description Initial State OFFSIZE [21:11] Virtual screen offset size (the number of half words). This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER RED Lookup Table Register Register Address R/W REDLUT 0X4D000020 R/W REDLUT REDVAL Description STN: Red lookup table register Bit [31:0] Description These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Dithering Mode Register Register Address R/W DITHMODE 0X4D00004C R/W DITHMODE Bit DITHMODE [18:0] Description STN: Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER Temp Palette Register Register Address R/W TPAL 0X4D000050 R/W TPAL TPALEN Description TFT: Temporary palette register. This register value will be video data at next frame. Bit [24] Description Temporary palette register enable bit. 0 = Disable TPALVAL [23:0] Reset Value 0x00000000 Initial state 0 1 = Enable Temporary palette value register.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Interrupt Pending Register Register Address R/W LCDINTPND 0X4D000054 R/W LCDINTPND INT_FrSyn Bit [1] Description Indicate the LCD interrupt pending register Description LCD frame synchronized interrupt pending bit. Reset Value 0x0 Initial state 0 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request. INT_FiCnt [0] LCD FIFO interrupt pending bit. 0 0 = The interrupt has not been requested.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER LCD Interrupt Mask Register Register Address R/W LCDINTMSK 0X4D00005C R/W LCDINTMSK FIWSEL Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. Bit Description [2] Determine the trigger level of LCD FIFO. 0 = 4 words INT_FrSyn [1] Reset Value 0x3 Initial state 1 = 8 words Mask LCD frame synchronized interrupt. 1 0 = The interrupt service is available. 1 = The interrupt service is masked.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR TCON Control Register Register Address R/W TCONSEL 0X4D000060 R/W Description Reset Value This register controls the LPC3600/LCC3600 modes.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate. The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 x 160 x 80 x 1/4 = 512 kHz CLKVAL = 58, VCLK = 517KHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200 Note The higher the system load is, the lower the CPU performance.
S3C2440A RISC MICROPROCESSOR LCD CONTROLLER Gray Level Selection Guide The S3C2440A LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depends on LCD's own characteristics, the user has to select an appropriate gray level after viewing all gray levels on user's own LCD.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention.
S3C2440A RISC MICROPROCESSOR 16 ADC AND TOUCH SCREEN INTERFACE ADC & TOUCH SCREEN INTERFACE OVERVIEW The 10-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down mode is supported.
ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of A/D converter and Touch Screen Interface. Note that the A/D converter device is a recycling type. AVDD Touch Screen Pads control AGND Pullup XP XM note YP YM ADC interface 8:1 A/D MUX Converter &Touch Screen Control note INT_ADC A[3:0] ADC input control Interrupt Generation INT_TC Waiting for Interrupt Mode Figure 16-1.
S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE FUNCTION DESCRIPTIONS A/D Conversion Time When the GCLK frequency is 50MHz and the prescaler value is 49, total 10-bit conversion time is as follows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1MHz / 5cycles) = 1/200KHz = 5 us NOTE This A/D converter was designed to operate at maximum 2.5MHz clock, so the conversion rate can go up to 500 KSPS. Touch Screen Interface Mode 1.
ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With polling method, by checking the ADCCON[15] - end of conversion flag-bit, the read time from ADCDAT register can be determined. 2.
S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL REGISTER (ADCCON) Register Address R/W Description Reset Value ADCCON 0x5800000 R/W ADC Control Register 0x3FC4 ADCCON Bit Description ECFLG [15] End of conversion flag(Read only) 0 = A/D conversion in process 1 = End of A/D conversion 0 PRSCEN [14] A/D converter prescaler enable 0 0 = Disable 1 = Enable A/D converter prescaler value Data value: 0 ~ 255 NOTE: ADC Fr
ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC) Register Address R/W Description Reset Value ADCTSC 0x5800004 R/W ADC Touch Screen Control Register 0x58 ADCTSC Bit Description Initial State UD_SEN [8] Detect Stylus Up or Down status. 0 = Detect Stylus Down Interrupt Signal. 1 = Detect Stylus Up Interrupt Signal. 0 YM_SEN [7] YM Switch Enable 0 = YM Output Driver Disable. 1 = YM Output Driver Enable.
S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC START DELAY REGISTER (ADCDLY) Register Address R/W Description Reset Value ADCDLY 0x5800008 R/W ADC Start or Interval Delay Register 0x00ff ADCDLY Bit DELAY [15:0] Description 1) Normal Conversion Mode, XY Position Mode, Auto Position Mode. → ADC conversion start delay value. 2) Waiting for Interrupt Mode. When Stylus Down occurs at SLEEP MODE, generates Wake-Up signal, having interval(several ms), for Exiting SLEEP MODE.
ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC CONVERSION DATA REGISTER (ADCDAT0) Register Address R/W ADCDAT0 0x580000C R Description ADC Conversion Data Register Reset Value - ADCDAT0 Bit Description Initial State UPDOWN [15] Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = Stylus up state. - AUTO_PST [14] Automatic sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion.
S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC CONVERSION DATA REGISTER (ADCDAT1) Register Address R/W ADCDAT1 0x5800010 R Description ADC Conversion Data Register Reset Value - ADCDAT1 Bit Description Initial State UPDOWN [15] Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = Stylus up state. - AUTO_PST [14] Automatically sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion.
ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR NOTES 16-10
S3C2440A RISC MICROPROCESSOR 17 REAL TIME CLOCK REAL TIME CLOCK OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation. The data include the time by second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 KHz crystal and also can perform the alarm function.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TICNT TIME TICK Time Tick Generator 128 Hz 215 Clock Divider RTCRST Reset Register Leap Year Generator XTIrtc 1 Hz SEC MIN HOUR DAY DATE MON YEAR XTOrtc Control Register Alarm Generator RTCCON RTCALM PMWKUP INT_RTC Figure 17-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR The Leap Year Generator can determine the last date of each month out of 28, 29, 30, or 31, based on data from BCDDATE, BCDMON, and BCDYEAR.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power-off mode or normal operation mode. In normal operation mode, the alarm interrupt (INT_RTC) is activated. In the power-off mode, the power management wakeup (PMWKUP) signal is activated as well as the INT_RTC. The RTC alarm register (RTCALM) determines the alarm enable/disable status and the condition of the alarm time setting.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Please note that the RTCALM register generates the alarm signal through both INT_RTC and PMWKUP in power down mode, but only through INT_RTC in the normal operation mode.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR ALARM SECOND DATA (ALMSEC) REGISTER Register ALMSEC ALMSEC Address R/W 0x57000054(L) 0x57000057(B) R/W (by byte) Description Alarm second data register Bit Description Reset Value 0x0 Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK ALARM DATE DATA (ALMDATE) REGISTER Register ALMDATE ALMDATE Address R/W 0x57000060(L) 0x57000063(B) R/W (by byte) Description Reset Value Alarm date data register 0x01 Description Initial State Bit Reserved [7:6] 00 DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR BCD SECOND (BCDSEC) REGISTER Register BCDSEC BCDSEC SECDATA Address R/W 0x57000070(L) 0x57000073(B) R/W (by byte) Description BCD second register Bit Description Reset Value Undefined Initial State [6:4] BCD value for second.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK BCD DATE (BCDDATE) REGISTER Register BCDDATE BCDDATE Address R/W 0x5700007C(L) 0x5700007F(B) R/W (by byte) Description BCD date register Bit Description Reset Value Undefined Initial State Reserved [7:6] - DATEDATA [5:4] BCD value for date.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR BCD YEAR (BCDYEAR) REGISTER Register BCDYEAR BCDYEAR YEARDATA 17-10 Address R/W 0x57000088(L) 0x5700008B(B) R/W (by byte) Bit [7:0] Description BCD year register Description BCD value for year.
S3C2440A RISC MICROPROCESSOR 18 WATCHDOG TIMER WATCHDOG TIMER OVERVIEW The S3C2440A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles.
WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again. MUX WTDAT Interrupt 1/16 1/32 PCLK WTCNT (Down Counter) 8-bit Prescaler 1/64 Reset Signal Generator RESET 1/128 WTCON[15:8] WTCON[4:3] WTCON[2] WTCON[0] Figure 18-1.
S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output.The Watchdog timer is used to resume the S3C2440A restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled.
WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out. In this case, the value of WTDAT will be automatically reloaded into WTCNT.
S3C2440A RISC MICROPROCESSOR 19 MMC/SD/SDIO CONTROLLER MMC/SD/SDIO Controller FEATURES SD Memory Card Spec(ver 1.0) / MMC Spec(2.11) compatible SDIO Card Spec(Ver 1.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SD OPERATION A serial clock line synchronizes shifting and sampling of the information on the five data lines. The transmission frequency is controlled by making the appropriate bit settings to the SDIPRE register. You can modify its frequency to adjust the baud rate data register value. Programming Procedure (common) To program the SDI modules, follow these basic steps: 1. Set SDICON to configure properly with clock & interrupt enable 2.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDIO OPERATION There are two functions of SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. And two functions have the steps and conditions like below. SDIO Interrupt In SD 1bit mode, Interrupt is received through all range from RxDAT[1] pin.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SDI SPECIAL REGISTERS SDI Control Register(SDICON) Register SDICON Address 0x5A000000 SDICON Reserved SDMMC Reset (SDreset) Bit [31:9] [8] Reserved Clock Type (CTYP) [7:6] [5] Byte Order Type(ByteOrder) [4] Receive SDIO Interrupt from card (RcvIOInt) [3] Read Wait Enable(RWaitEn) [2] Reserved Clock Out Enable (ENCLK) [1] [0] R/W R/W Description SDI Control Register Description Reset whole sdmmc block. This bit is automatically cleared.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Command Argument Register(SDICmdArg) Register SDICmdArg SDICmdArg CmdArg Address 0x5A000008 Bit [31:0] R/W R/W Description SDI Command Argument Register Description Command Argument Reset Value 0x0 Initial Value 0x00000000 SDI Command Control Register(SDICmdCon) Register SDICmdCon Address 0x5A00000C SDICommand Reserved Abort Command (AbortCmd) Bit [31:13] [12] Command with Data (WithData) [11] LongRsp [10] WaitRsp [9] Command Start(CM
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SDI Command Status Register(SDICmdSta) Register SDICmdSta Address 0x5A000010 SDICmdSta Reserved Response CRC Fail(RspCrc) Bit [31:13] [12] R/C Command Sent (CmdSent) [11] R/C Command Time Out (CmdTout) [10] R/C Response Receive End (RspFin) [9] R/C CMD line progress On (CmdOn) [8] RspIndex [7:0] R/W R/(C) Description SDI Command Status Register Reset Value 0x0 Description Initial Value CRC check failed when command response received.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Response Register 2(SDIRSP2) Register SDIRSP2 SDIRSP2 Response2 Address 0x5A00001C Bit [31:0] R/W R Description SDI Response Register 2 Description unused(short), card status[63:32](long) Reset Value 0x0 Initial Value 0x00000000 SDI Response Register 3(SDIRSP3) Register SDIRSP3 SDIRSP3 Response3 Address 0x5A000020 Bit [31:0] R/W R Description SDI Response Register 3 Description unused(short), card status[31:0](long) Reset Value 0x0 Initial
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SDI Data Control Register(SDIDatCon) Register SDIDatCon SDIDatCon Reserved Burst4 enable (Burst4) Address 0x5A00002C Bit [31:25] [24] R/W R/W Description SDI Data control Register Description Reset Value 0x0 Initial Value 0 Enable Burst4 mode in DMA mode. This bit should be set only when Data Size is word.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Data Remain Counter Register(SDIDatCnt) Register SDIDatCnt Address 0x5A000030 SDIDatCnt Reserved BlkNumCnt BlkCnt Bit [31:24] [23:12] [11:0] R/W R Description SDI Data Remain Counter Register Description Remaining Block number Remaining data byte of 1 block Reset Value 0x0 Initial Value 0x000 0x000 SDI Data Status Register(SDIDatSta) Register SDIDatSta Address 0x5A000034 SDIDatSta Reserved No Busy(NoBusy) Bit [31:12] [11] R/C Read Wait Re
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SDI FIFO Status Register(SDIFSTA) Register SDIFSTA Address 0x5A000038 SDIFSTA Reserved FIFO Reset(FRST) Bit [31:16] [16] C FIFO Fail error (FFfail) [15:14] R/C FIFO available Detect for Tx (TFDET) [13] FIFO available Detect for Rx (RFDET) [12] Tx FIFO Half Full (TFHalf) [11] Tx FIFO Empty (TFEmpty) [10] Rx FIFO Last Data Ready (RFLast) [9] R/C Rx FIFO Full (RFFull) [8] Rx FIFO Half Full (RFHalf) [7] R/W R/(C) Description SDI FIFO Sta
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER SDI Interrupt Mask Register(SDIIntMsk) Register SDIIntMsk Address 0x5A00003C SDIIntMsk Reserved NoBusy Interrupt Enable (NoBusyInt) Bit [31:19] [18] RspCrc Interrupt Enable (RspCrcInt) [17] CmdSent Interrupt Enable (CmdSentInt) [16] CmdTout Interrupt Enable (CmdToutInt) [15] RspEnd Interrupt Enable (RspEndInt) [14] RWaitReq Interrupt Enable (RWReqInt) [13] IOIntDet Interrupt Enable (IntDetInt) [12] FFfail Interrupt Enable (FFfailInt) [11
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR SDI Data Register(SDIDAT) Register SDIDAT SDIDAT Data Register Address 0x5A000040, 44, 48, 4C(Li/W, Li/HW, Li/B, Bi/W) 0x5A000041(Bi/HW), 0x5A000043(Bi/B) Description SDI Data Register Description This field contains the data to be transmitted or received over the SDI channel * (Li/W, Li/HW, Li/B) : Access by Word/HalfWord//Byte unit when endian mode is Little * (Bi/W) : Access by Word unit when endian mode is Big * (Bi/HW) : Access by HalfWord unit
S3C2440A RISC MICROPROCESSOR 20 IIC-BUS INTERFACE IIC-BUS INTERFACE OVERVIEW The S3C2440A RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C2440A RISC microprocessors can receive or transmit serial data to or from slave devices.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register Shift Register (IICDS) Data Bus Figure 20-1.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE The S3C2440A IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave transmitter mode — Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in Slave mode.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE SDA Acknowledgement Signal from Receiver MSB 2 1 SCL 7 8 9 Acknowledgement Signal from Receiver 1 2 9 ACK S Byte Complete, Interrupt within Receiver Clock Line Held Low by receiver and/or transmitter Figure 20-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written. The S3C2440A should hold the interrupt to identify the completion of current data transfer.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output START Master Tx mode has been configured. Write slave address to IICDS. Write 0xF0 (M/T Start) to IICSTAT. The data of the IICDS is transmitted. ACK period and then interrupt is pending.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop? Y N Read a new data from IICDS. Write 0x90 (M/R Stop) to IICSTAT. Clear pending bit to resume. Clear pending bit . SDA is shifted to IICDS. Wait until the stop condition takes effect.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? N Y The IIC address match interrupt is generated. Write data to IICDS. Clear pending bit to resume. Stop? Y N The data of the IICDS is shifted to SDA. END Interrupt is pending.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? N Y The IIC address match interrupt is generated. Read data from IICDS. Clear pending bit to resume. Stop? Y N SDA is shifted to IICDS. END Interrupt is pending.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register IICCON Address R/W 0x54000000 R/W IICCON Bit Acknowledge generation (1) [7] Description IIC-Bus control register Description IIC-bus acknowledge enable bit. Reset Value 0x0X Initial State 0 0 : Disable 1 : Enable In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register IICSTAT Address R/W Description 0x54000004 R/W IIC-Bus control/status register IICSTAT Mode selection Bit [7:6] Description IIC-bus master/slave Tx/Rx mode select bits.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register IICADD IICADD Slave address Address R/W 0x54000008 R/W Description IIC-Bus address register Bit [7:0] Description 7-bit slave address, latched from the IIC-bus. When serial output enable = 0 in the IICSTAT, IICADD is write-enabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register IICLC IICLC Filter Enable Address R/W 0x54000010 R/W Description Reset Value IIC-Bus multi-master line control register 0x00 Bit Description Initial State [2] IIC-bus filter enable bit. When SDA port is operating as input, this bit should be High. This filter can prevent from occurred error by a glitch during double of PCLK time.
S3C2440A RISC MICROPROCESSOR 21 IIS-BUS INTERFACE IIS-BUS INTERFACE OVERVIEW Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound. The S3C2440A Inter-IC Sound (IIS) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for minidisc and portable applications.
IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR BLOCK DIAGRAM TxFIFO ADDR DATA BRFC SFTR SD CNTL RxFIFO PCLK CHNC SCLK IPSR_A SCLKG IPSR_B LRCK CDCLK MPLLin Figure 21-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine.
S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE DMA TRANSFER In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously.
IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR LRCK LEFT RIGHT LEFT SCLK MSB (1st) SD 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) N-1th Bit LSB (last) IIS-bus Format (N=8 or 16) LRCK LEFT RIGHT SCLK SD MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit MSB-justified Format (N=8 or 16) Figure 21-2.
S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL (IISCON) REGISTER Register IISCON Address 0x55000000 (Li/HW, Li/W, Bi/W) 0x55000002 (Bi/HW) IISCON R/W Description Reset Value R/W IIS control register 0x100 Bit Description Initial State Left/Right channel index (Read only) [8] 0 = Left 1 = Right 1 Transmit FIFO ready flag (Read only) [7] 0 = Empty 1 = Not empty 0 Receive FIFO ready flag (Read only) [6] 0 = Full 1 = Not full 0 Transmit D
IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR IIS MODE REGISTER (IISMOD) REGISTER Register Address R/W Description Reset Value IISMOD 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W IIS mode register 0x0 IISMOD Master Clock Select Master/slave mode select Bit [9] [8] Description Master clock select 0 = PCLK Initial State 0 1 = MPLLin 0 = Master mode (IISLRCK and IISCLK are output mode). 1 = Slave mode (IISLRCK and IISCLK are input mode).
S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE IIS PRESCALER (IISPSR) REGISTER Register IISPSR Address 0x55000008 (Li/HW, Li/W, Bi/W) 0x5500000A (Bi/HW) IISPSR Bit Prescaler control A [9:5] R/W Description Reset Value R/W IIS prescaler register 0x0 Description Data value: 0 ~ 31 Initial State 00000 Note: Prescaler A makes the master clock that is used the internal block and division factor is N+1.
IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR IIS FIFO CONTROL (IISFCON) REGISTER Register Address R/W Description Reset Value IISFCON 0x5500000C (Li/HW, Li/W, Bi/W) 0x5500000E (Bi/HW) R/W IIS FIFO interface register 0x0 IISFCON Bit Description Initial State Transmit FIFO access mode select [15] 0 = Normal 1 = DMA 0 Receive FIFO access mode select [14] 0 = Normal 1 = DMA 0 Transmit FIFO [13] 0 = Disable 1 = Enable 0 Receive FIFO [12] 0 = Disable 1 = Enable 0 Transmit FIFO
S3C2440A RISC MICROPROCESSOR 22 SPI SPI OVERVIEW The S3C2440A Serial Peripheral Interface (SPI) can interface with the serial data transfer. The S3C2440A includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings.
SPI S3C2440A RISC MICROPROCESSOR BLOCK DIAGRAM Data Bus SPIMISO 0 MSB Slave Master Master Slave Tx 8bit Shift Reg 0 MSB 8 LSB Rx 8bit Shift Reg 0 Clock PCLK SPI Clock (Master) 8bit Prescaler 0 CLOCK Logic 0 CPOL CPHA Prescaler Register 0 MOSI SPICLK 0 SCK /SS Slave MULF DCOL SPIMOSI 0 nSS 0 Status Register 0 REDY Slave Master MISO Pin Control Logic 0 LSB 8 MSTR INT 0 / INT 1 APB I/F 0 REQ0 / REQ1 (INT DMA 0) ACK0 / ACK1 SPIMISO 1 MSB Slave Master Master Slave Tx 8bit
S3C2440A RISC MICROPROCESSOR SPI SPI OPERATION Using the SPI interface, S3C2440A can send/receive 8-bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information. When the SPI is the master, transmission frequency can be controlled by setting the appropriate bit in SPPREn register. You can modify its frequency to adjust the baud rate data register value. When the SPI is a slave, other master supplies the clock.
SPI S3C2440A RISC MICROPROCESSOR SPI TRANSFER FORMAT The S3C2440A supports 4 different formats to transfer data. Figure 22-2 shows the four waveforms for SPICLK.
S3C2440A RISC MICROPROCESSOR SPI TRANSMITTING PROCEDURE FOR DMA 1. SPI is configured as DMA mode. 2. DMA is configured properly. 3. SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0. 7. SPI is configured as interrupt or polling mode with SMOD bits. RECEIVING PROCEDURE FOR DMA 1. SPI is configured as DMA start with SMOD bits and TAGD bit set. 2. DMA is configured properly. 3. SPI receives 1byte data from card.
SPI S3C2440A RISC MICROPROCESSOR SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register Address R/W Description Reset Value SPCON0 0x59000000 R/W SPI channel 0 control register 0x00 SPCON1 0x59000020 R/W SPI channel 1 control register 0x00 SPCONn Bit SPI Mode Select (SMOD) [6:5] SCK Enable [4] Determine how SPTDAT is read/written 00 = polling mode 10 = DMA mode (ENSCK) Master/Slave Select (MSTR) Description [3] 0 1 = enable Determine the desired mode (master or slave).
S3C2440A RISC MICROPROCESSOR SPI SPI STATUS REGISTER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI channel 0 status register 0x01 SPSTA1 0x59000024 R SPI channel 1 status register 0x01 SPSTAn Bit Reserved [7:3] Data Collision Error Flag (DCOL) [2] Description Initial State This flag is set if the SPTDATn is written or SPRDATn is read while a transfer is in progress and cleared by reading the SPSTAn.
SPI S3C2440A RISC MICROPROCESSOR The SPIMISO (MISO) and SPIMOSI (MOSI) data pins are used for transmitting and receiving serial data. When SPI is configured as a master, SPIMISO (MISO) is the master data input line, SPIMOSI (MOSI) is the master data output line, and SPICLK (SCK) is the clock output line. When SPI becomes a slave, these pins perform reverse roles. In a multiple-master system, SPICLK (SCK) pins, SPIMOSI (MOSI) pins, and SPIMISO (MISO) pins are tied to configure a group respectively.
S3C2440A RISC MICROPROCESSOR 23 CAMERA INTERFACE CAMERA INTERFACE OVERVIEW This chapter will explain the specification and defines the camera interface. CAMIF (CAMera InterFace) within the S3C2440A consists of 7 parts – pattern mux, capturing unit, preview scaler, codec scaler, preview DMA, codec DMA, and SFR. The CAMIF supports ITU-R BT.601/656 YCbCr 8-bit standard. Maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling) and two scalers exist.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE BLOCK DIAGRAM T_patternMux CamI f SFR YCbCr 4:2:X CatchCam ITU-R BT 601/656 YCbCr 4:2:2 Preview Scaler & RGB Formatter Codec Scaler Preview DMA Codec DMA AHB bus Figure 23-1 CAMIF Overview 23-2
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM XG jht}zuj }G jhtoylm jhtoylmG OXoP o¡G jhtwjsr _TG jhtkh{h ^aW j j j j j WW WW Figure 23-2 ITU-R BT 601 Input Timing Diagram jhtwjsr jhtkh{h ^aW mm WW WW j j mm }G G }G G wG Figure 23-3 ITU-R BT 656 Input Timing Diagram There are two timing reference signals in ITU-R BT 656 format, one is at t
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE Table 23-2 Video Timing Reference Codes of ITU-656 Format Data bit number First word Second word Third word Fourth word 9 (MSB) 1 0 0 1 8 1 0 0 F 7 1 0 0 V 6 1 0 0 H 5 1 0 0 P3 4 1 0 0 P2 3 1 0 0 P1 2 1 0 0 P0 1 (NOTE) 1 0 0 0 0 1 0 0 0 For compatibility with existing 8-bit interfaces, the values of bits D1 and D0 are not defined.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OPERATION TWO DMA PATHS CAMIF has 2 DMA paths. P-path (Preview path) and C-path (Codec path) are separated from each other on the AHB bus. In view of the system bus, both the paths are independent. The P-path stores the RGB image data into memory for PIP. The C-path stores the YCbCr 4:2:0 or 4:2:2 image data into memory for Codec as MPEG-4, H.263, etc.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE mal-functioning USB PLL 96 MHz UPLL S3C2440A MPLL fmpll fUSB Normally use CAMCLKOUT fUSB /d Divide Counter 1/1 ~ 1/16 fmpll /d Schmit-triggered Level-shifter External Camera Processor Divide Counter CAMIF HCLK CAMPCLK External MCLK Figure 23-5 CAMIF Clock Generation [T mG G OzkyhtP wTGyniGXG wTGyniGYG wTGyniGZG wT yni [a[a[ p{|T]WXV]\] jj [aYaY _T jGp jT [aYaWSY wTGyniG[G hoiG
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE MEMORY STORING METHOD The little-endian method in codec path is used to store in the frame memory. The pixels are stored from LSB to MSB side. AHB bus carries 32-bit word data. So, CAMIF makes each of the Y-Cb-Cr words in little-endian style. For preview path, two different formats exist. One pixel (Color 1 pixel) is one word for RGB 24-bit format. Otherwise, two pixels are one word for RGB 16-bit format. Please refer the following figure.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can occur anywhere in the frame period. But, it is recommended that you set it at the CAMVSYNC “L” state first and the CAMVSYNC information can be read from the status SFR (Please see next page). All command include ImgCptEn, is valid at CAMVSYNC falling edge.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR LAST IRQ IRQ except LastIRQ is generated before image capturing. Last IRQ which means capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and ,as mentioned, SFR setting in ISR is for next frame command. So, for adequate last IRQ, you should follow next sequence between LastIRQEn and ImgCptEn /ImgCptEn_CoSc /ImgCptEnPrSC.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE SPECIAL REGISTERS SOURCE FORMAT REGISTER Register Address R/W Description Reset Value CISRCFMT 0x4F000000 RW Input Source Format Register 0 CISRCFMT Bit ITU601_656n [31] Description 0 = ITU-R BT.656 YCbCr 8-bit mode enable 1 = ITU-R BT.601 YCbCr 8-bit mode enable Initial State 0 Cb,Cr Value Offset Control.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER Register Address R/W Description Reset Value CIWDOFST 0x4F000004 RW Window Offset Register 0 CIWDOFST Bit Description Initial State WinOfsEn [31] 0 = No offset 1 = Window offset enable 0 ClrOvCoFiY [30] 0 = Normal 1 = Clear the overflow indication flag of input CODEC FIFO Y 0 Window Horizontal Offset (the number which is the horizontal pixels except WinHorOfst * 2, must be multiple of 8) * WinHorOfst >= (SourceHsize
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER Register Address R/W Description Reset Value CIGCTRL 0x4F000008 RW Global Control Register 0 CIGCTRL Bit Description Initial State SwRst [31] Camera Interface Software Reset 0 CamRst [30] External Camera Processor Reset or Power Down 0 Reserved [29] This bit is reserved and the value must be 1. 1 This register should be set only at ITU-T 601 8-bit mode. It is not allowed with ITU-T 656 mode. (max.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE Y3 START ADDRESS REGISTER Register CICOYSA3 CICOYSA3 CICOYSA3 Address R/W 0x4F000020 RW Description Reset Value Y 3 frame start address for codec DMA 0 rd Bit [31:0] Description Initial State rd Y 3 frame start address for codec DMA 0 Y4 START ADDRESS REGISTER Register CICOYSA4 CICOYSA4 CICOYSA4 Address R/W 0x4F000024 RW Description Reset Value Y 4 frame start address for codec DMA 0 th Bit [31:0] Description Initial State th Y 4
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CB4 START ADDRESS REGISTER Register CICOCBSA4 CICOCBSA4 CICOCBSA4 Address R/W 0x4F000034 RW Description Reset Value Cb 4 frame start address for codec DMA 0 th Bit [31:0] Description Initial State th Cb 4 frame start address for codec DMA 0 CR1 START ADDRESS REGISTER Register CICOCRSA1 CICOCRSA1 CICOCRSA1 Address R/W 0x4F000038 RW Description Reset Value Cr 1 frame start address for codec DMA 0 st Bit [31:0] Description Initial Stat
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CODEC TARGET FORMAT REGISTER Register Address R/W Description Reset Value CICOTRGFMT 0x4F000048 RW Target image format of codec DMA 0 CICOTRGFMT Bit Description Initial State [31] 0 = YCbCr 4:2:0 codec scaler input image format. In this case, horizontal line decimation is performed before codec scaler. (normally used) 1 = YCbCr 4:2:2 codec scaler input image format. 0 Out422_Co [30] 0 = YCbCr 4:2:0 codec scaler output image format.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER Register Address R/W Description Reset Value CICOCTRL 0x4F00004C RW Codec DMA control related 0 CICOCTRL Bit Description Initial State Yburst1_Co [23:19] Main burst length for codec Y frames 0 Yburst2_Co [18:14] Remained burst length for codec Y frames 0 Cburst1_Co [13:9] Main burst length for codec Cb/Cr frames 0 Cburst2_Co [8:4] Remained burst length for codec Cb/Cr frames 0 LastIRQEn_Co [2] 0 = norm
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE REGISTER SETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_Width satisfy the word boundary constraints such that the number of horizontal pixel can be represented to kn where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 image, respectively. TargetHsize should not be larger than SourceHsize. Similarly, TargetVsize should not be larger than SourceVsize.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE If ( SRC_Height >= 64 × DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 × DST_Height) { PreVerRatio_xx = 32; V_Shift = 5; } else if (SRC_Height >= 16 × DST_Height) { PreVerRatio_xx = 16; V_Shift = 4; } else if (SRC_Height >= 8 × DST_Height) { PreVerRatio_xx = 8; V_Shift = 3; } else if (SRC_Height >= 4 × DST_Height) { PreVerRatio_xx = 4; V_Shift = 2; } else if (SRC_Height >= 2 × DST_Height) { PreVerRatio_xx = 2; V_Shift =
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CODEC MAIN-SCALER CONTROL REGISTER Register Address R/W Description Reset Value CICOSCCTRL 0x4F000058 RW Codec main-scaler control 0 CICOSCCTRL Bit Description Initial State ScalerBypass_Co [31] Codec scaler bypass for upper 2048 x 2048 size (In this case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0, but ImgCptEn should be 1. It is not allowed to capture preview image.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE CODEC STATUS REGISTER Register Address R/W Description Reset Value CICOSTATUS 0x4F000064 R Codec path status 0 CICOSTATUS Bit Description Initial State OvFiY_Co [31] Overflow state of codec source FIFO Y 0 OvFiCb_Co [30] Overflow state of codec source FIFO Cb 0 OvFiCr_Co [29] Overflow state of codec source FIFO Cr 0 VSYNC [28] Camera VSYNC (This bit can be referred by CPU for first SFR setting.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE RGB3 START ADDRESS REGISTER Register CIPRCLRSA3 CIPRCLRSA3 CIPRCLRSA3 Address R/W 0x4F000074 RW Description Reset Value RGB 3 frame start address for preview DMA 0 rd Bit [31:0] Description Initial State rd RGB 3 frame start address for preview DMA 0 RGB4 START ADDRESS REGISTER Register CIPRCLRSA4 CIPRCLRSA4 CIPRCLRSA4 Address R/W 0x4F000078 RW Description Reset Value RGB 4 frame start address for preview DMA 0 Bit [31:0] th Descri
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW DMA CONTROL REGISTER Register Address R/W Description Reset Value CIPRCTRL 0x4F000080 RW Preview DMA control related 0 CIPRCTRL Bit Description Initial State RGBburst1_Pr [23:19] Main burst length for preview RGB frames 0 RGBburst2_Pr [18:14] Remained burst length for preview RGB frames 0 LastIRQEn_Pr [2] 0 = Normal 1 = Enable last IRQ at the end of frame capture. (This bit is cleared automatically.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW PRE-SCALER CONTROL REGISTER 2 Register Address R/W Description Reset Value CIPRSCPREDST 0x4F000088 RW Preview pre-scaler destination format 0 CIPRSCPREDST Bit Description Initial State PreDstWidth_Pr [27:16] Destination width for preview pre-scaler 0 PreDstHeight_Pr [11:0] Destination height for preview pre-scaler 0 PREVIEW MAIN-SCALER CONTROL REGISTER Register Address R/W Description Reset Value CIPRSCCTRL 0x4F00008C RW P
S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW STATUS REGISTER Register Address R/W Description Reset Value CIPRSTATUS 0x4F000098 R Preview path status 0 CIPRSTATUS Bit Description Initial State OvFiCb_Pr [31] Overflow state of preview source FIFO Cb 0 OvFiCr_Pr [30] Overflow state of preview source FIFO Cr 0 FrameCnt_Pr [27:26] Frame count of preview DMA 0 FlipMd_Pr [24:23] Flip mode of preview DMA 0 ImgCptEn_PrSC [21] Image capture enable of preview path 0 IMAGE
S3C2440A RISC MICROPROCESSOR 24 AC97 CONTROLLER AC97 CONTROLLER OVERVIEW The AC97 Controller Unit of the S3C2440A supports AC97 revision 2.0 features. AC97 Controller communicates with AC97 Codec using an audio controller link (AC-link). Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER OPERATION BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of the S3C2440A AC97 Controller. The AC97 signals form the AClink, which is a point-to-point synchronous serial interconnect that supports full-duplex data transfers. All digital audio streams and command/status information are communicated over the AC-link.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER INTERNAL DATA PATH Figure 24-2 shows the internal data path of the S3C2440A AC97 Controller. It has stereo Pulse Code Modulated (PCM) In, Stereo PCM Out and mono Mic-in buffers, which consist of 16-bit, 16 entries buffer. Also it has a 20-bit I/O shift register via AC-link.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR OPERATION FLOW CHART System reset or Cold reset Set GPIO and Release INTMSK/SUBINTMSK bits Enable Codec Ready interrupt No No Time out condition ? Codec Ready interrupt ? Yes Controller off Disable Codec Ready interrupt DMA operation or PIO (Interrupt or Polling) operation Figure 24-3 AC97 Operation Flow Chart 24-4
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER AC-LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S3C2440A AC97 Controller. The AC-link is a full-duplex, fixed-clock, PCM digital stream. It employs a time division multiplexing (TDM) scheme to handle control register access and multiple input and output audio streams. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR AC-LINK INPUT FRAME (SDATA_IN) Tag Phase SYNC Data Phase AC '97 samples SYNC assertion here AC '97 Controller samples first SDATA_IN bit of frame here BIT_CLK SDATA_OUT Codec Ready Slot(1) Slot(2) Slot(12) "0" "0" "0" 19 0 START of Data phase Slot# 1 END of previous Audio Frame 19 0 END of Data Frame Slot# 12 Figure 24-6 AC-link Input Frame AC97 POWERDOWN SYNC BIT_CLK SDATA_OUT slot 12 prev.frame TAG SDATA_IN slot 12 prev.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER Waking up the AC-link - Wake Up Triggered by the AC97 Controller AC-link protocol is provided for a cold AC97 reset and a warm AC97 reset. The current power-down state ultimately dictates which AC97 reset is used. Registers must stay in the same state during all power-down modes unless a cold AC97 reset is performed. In a cold AC97 reset, the AC97 registers are initialized to their default values.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER SPECIAL REGISTERS AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) Register Address R/W Description Reset Value AC_GLBCTRL 0x5B000000 R/W AC97 Global Control Register 0x000000 AC_GLBCTRL Reserved Codec Enable Bit Description [31:23] Ready Interrupt [22] PCM Out Channel Underrun Interrupt Enable [21] PCM In Channel Overrun Interrupt Enable [20] MIC In Channel Overrun Interrupt Enable [19] PCM Out Channel Threshold Interrupt Enable
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT) Register Address R/W Description Reset Value AC_GLBSTAT 0x5B000004 R AC97 Global Status Register 0x00000000 AC_GLBSTAT Bit Reserved Description Initial State [31:23] Codec Ready Interrupt 0x00 [22] 0 : Not requested 1 : Requested 0 [21] 0 : Not requested 1 : Requested 0 PCM In Channel Overrun Interrupt [20] 0 : Not requested 1 : Requested 0 MIC In Channel Overrun Interrupt [19] 0 : Not re
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) Register Address R/W Description Reset Value AC_CODEC_STAT 0x5B00000C R AC97 Codec Status Register 0x00000000 Description Initial State AC_CODEC_STAT Bit Reserved [31:23] Address [22:16] CODEC Status Address Data [15:0] CODEC Status Data 0x00 0x00 0x0000 Note: If you want to read data from AC97 codec register via the AC_CODEC_STAT register, you should follow these steps. 1.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR) Register Address R/W Description Reset Value AC_MICADDR 0x5B000014 R AC97 Mic In Channel FIFO Address Register 0x00000000 AC_MICADDR Bit Reserved [31:20] Read Address [19:16] Reserved [15:4] Write Address [3:0] Description Initial State 0000 MIC in channel FIFO read address 0000 0x000 MIC in channel FIFO write address 0000 AC97 PCM OUT/IN CHANNEL FIFO DATA REGISTER (AC_PCMDATA) Reg
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR NOTES 24-12
S3C2440A RISC MICROPROCESSOR 25 BUS PRIORITIES BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. BUS PRIORITY MAP The S3C2440A holds 13 bus masters. They include DRAM refresh controller, LCD_DMA, CAMIF DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC) and ARM920T. The following list shows the priorities among these bus masters after a reset: 1.
BUS PRIORITIES S3C2440A RISC MICROPROCESSOR NOTES 25-2
S3C2440A RISC MICROPROCESSOR 26 MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS 0.15 C x 2 A 14.00 289-FBGA-1414 SAMSUNG 14.00 B 0.15 C x 2 1.22 0.35 + 0.05 0.10 C 0.45 0.12 MAX ±0.05 C TOLERANCE ±0.
MECHANICAL DATA S3C2440A RISC MICROPROCESSOR 14.00 A1 INDEX MARK 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.80 0.80 289 - 0.45 14.00 0.80 x 16 = 12.80 ± 0.05 A B C D E F G H J K L M N P R T U ± 0.05 0.15 M C A B 0.08 M C TOLERANCE Figure 26-2 289-FBGA-1414 Package Dimension 2 (Bottom View) The recommended land open size is 0.39 – 0.41mm diameter. 26-2 ± 0.
S3C2440A RISC MICROPROCESSOR 27 ELECTRICAL DATA ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 27-1 Absolute Maximum Rating Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Input (Latch-up) Current Storage Temperature Symbol Rating Unit VDDi 1.2V VDD 1.8 VDDOP 3.3V VDD 4.8 VDDMOP 1.8V/2.5V/3.0V/3.3V VDD 4.8 VDDRTC 1.8V/2.5V/3.0V/3.3V VDD 4.5 VDDADC 3.3V VDD 4.8 3.3V Input buffer 4.8 3.3V Interface / 5V Tolerant input buffer 6.5 3.3V Output buffer 4.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR RECOMMENDED OPERATING CONDITIONS Table 27-2 Recommended Operating Conditions Parameter Symbol DC Supply Voltage for Alive Block VDDalive VDDi DC Supply Voltage for Internal VDDiarm(1) VDDMPLL VDDUPLL VDDOP DC Supply Voltage for Memory interface VDDMOP DC Supply Voltage for Analog Core VDD DC Input Voltage Typ. Min Max 300MHz: 1.2V VDD 400MHz: 1.3V VDD 1.15 1.15 1.25 1.35 300MHz: 1.2V VDD 1.15 1.25 400MHz: 1.3V VDD 1.25 1.35 3.3V VDD 3.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA D.C. ELECTRICAL CHARACTERISTICS Table 27-3 and 27-4 defines the DC electrical characteristics for the standard LVCMOS I/O buffers. Table 27-3 Normal I/O PAD DC Electrical Characteristics ±0.2V, TA = -40 to 85 °C) Normal I/O PAD DC Electrical Characteristics for Memory (VDDMOP = 2.5V± Symbol VIH VIL Parameters Condition Typ. Max High level input voltage LVCMOS interface Low level input voltage LVCMOS interface 0.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Normal I/O PAD DC Electrical Characteristics for Memory (VDDMOP=3.0V± ±0.3V, 3.3V ± 0.3V, TA=-40 to 85 °C) Symbol VIH VIL Parameters Condition Typ. Max High level input voltage LVCMOS interface Low level input voltage LVCMOS interface 0.8 Switching threshold VT+ Schmitt trigger, positive-going threshold CMOS VT- Schmitt trigger, negative-going threshold CMOS 0.5VDD V V 2.0 0.8 V V High level input current Input buffer Unit V 2.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA Normal I/O PAD DC Electrical Characteristics for I/O (VDDOP = 3.3V ± 0.3V, TA = -40 to 85 °C) Symbol VIH VIL Parameters Condition Typ. Max High level input voltage LVCMOS interface Low level input voltage LVCMOS interface 0.8 Switching threshold VT+ Schmitt trigger, positive-going threshold CMOS VT- Schmitt trigger, negative-going threshold CMOS 0.5VDD V V 2.0 0.8 V V High level input current Input buffer Unit V 2.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27-4 USB DC Electrical Characteristics Symbol Parameter Condition VIH High level input voltage VIL Low level input voltage IIH High level input current Vin = 3.3V IIL Low level input current VOH VOL Min Max 2.5 Unit V 0.8 V -10 10 µA Vin = 0.0V -10 10 µA Static Output High 15K to GND 2.8 3.6 V Static Output Low 1.5K to 3.6V 0.3 V Table 27-5 S3C2440 Power Supply Voltage and Current Parameter Value Unit 1.3 / 3.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 400Mhz Power consumption 250 227mW Power[mW] 200 155mW Core Power 104% Up 150 Core Power 100 50 IO Power 139mW 68mW 87mW Total Power 46% Up 88mW 0 DVS(o) Using DVS DVS(x) without DVS Item NOTE: (Condition) Current measure condition: Play Battlife.wma(bit rate=64kbps) on PPC2003 SMDK2440. Core power: Without DVS : VDDiarm/VDDi/VDDupll/VDDmpll/VDDalive = 1.3V using DVS : VDDiarm/VDDi = 1.3V 1.0V, others 1.3V fixed.
ELECTRICAL DATA 27-8 S3C2440A RISC MICROPROCESSOR
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA A.C. ELECTRICAL CHARACTERISTICS tXTALCYC 1/2 VDD 1/2 VDD NOTE: Clock input is from the XTIpll pin. Figure 27-2 XTIpll Clock Timing Diagram tEXTCYC tEXTHIGH VIH 1/2 VDD tEXTLOW VIH VIL VIL VIH 1/2 VDD NOTE: Clock input is from the EXTCLK pin.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR HCLK (internal) tHC2CK CLKOUT (HCLK) tHC2SCLK SCLK Figure 27-5 HCLK/CLKOUT/SCLK in case when EXTCLK is used EXTCLK nRESET tRESW Figure 27-6 Manual Reset Input Timing Diagram 27-10
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK ... PLL is configured by S/W first time. tPLL Clock Disable VCO is adapted to new clock frequency. VCO output ... tRST2RUN ... FCLK MCU operates by XTIpll or EXTCLK clcok. FCLK is new frequency.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR EXTCLK XTIpll Clock Disable tOSC2 VCO Output Several slow clocks (XTIpll or EXTCLK) FCLK Power_OFF mode is initiated.
DATA '1' nBEx Tacc nOE nGCSx ADDR tROD tRCD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tROD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD HCLK tRDH ELECTRICAL DATA tRCD S3C2440A RISC MICROPROCESSOR Figure 27-9 ROM/SRAM Burst READ Timing Diagram (I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit) 27-13
tRDH tRDH tRDS DATA nBEx tRBED Tacc nOE nGCSx ADDR tROD tRCD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRAD tRAD tRAD tRAD tRAD tRAD tRAD HCLK tRDH tRDS tROD tRAD tRAD tRBED S3C2440A RISC MICROPROCESSOR tRCD ELECTRICAL DATA Figure 27-10 ROM/SRAM Burst READ Timing Diagram (II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit) 27-14
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA HCLK tHZD ADDR 'HZ' tHZD nGS 'HZ' tHZD nOE 'HZ' tXnBRQH tXnBRQS XnBREQ tXnBACKD tXnBACKD XnBACK Figure 27-11 External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0) 27-15
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs tROD nOE tROD Tcos Tacc nWBEx Toch '1' tRDS DATA tRDH Figure 27-12 ROM/SRAM READ Timing Diagram (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0) 27-16 Tcah
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs tROD nOE tROD Tcah Tcos Tacc Toch tRBED tRBED nBEx tRDS DATA tRDH Figure 27-13 ROM/SRAM READ Timing Diagram (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) 27-17
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD nWE tRWD Tcos Tacc tRWBED nWBEx Toch tRWBED Tcos Toch tRDD DATA Figure 27-14 ROM/SRAM WRITE Timing Diagram (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 27-18 tRDD
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA HCLK tRAD tRAD ADDR tRCD tRCD nGCSx Tacs Tcah tRWD nWE tRWD Tcos Tacc Toch tRBED tRBED nBEx tRDD tRDD DATA Figure 27-15 ROM/SRAM WRITE Timing Diagram (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1) 27-19
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR HCLK tRC ADDR nGCSx Tacs delayed Tacc = 6cycle nOE Tacs sampling nWait nWait DATA NOTE: The status of nWait is checked at (Tacc-1) cycle.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA HCLK tRAD tRAD ADDR tRCD nGCSx Tacs tROD nOE Tcos Tacc tRDS DATA tRDH Figure 27-18 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11) HCLK tRAD tRAD tRAD tRAD tRAD tRAD ADDR tRCD nGCSx tROD nOE Tacc Tpac tRDS Tpac tRDS Tpac tRDS Tpac tRDS tRDS DATA tRDH tRDH tRDH tRDH tRDH Figure 27-19 Masked-ROM Consecutive READ Timing Diagram (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11) 27-21
tSDH S3C2440A RISC MICROPROCESSOR tSWD tSRD DATA nWE nBEx nSCAS nSRAS nGCSx A10/AP ADDR/BA SCKE SCLK '1' tSAD tSAD tSCSD Trp Trcd tSCD tSBED Tcl tSDS ELECTRICAL DATA Figure 27-20 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit) 27-22
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tHZD SCLK tHZD SCKE '1' tHZD 'HZ' 'HZ' ADDR/BA 'HZ' tHZD A10/AP 'HZ' tHZD nGCSx 'HZ' tHZD nSRAS 'HZ' tHZD nSCAS tHZD nBEx 'HZ' 'HZ' tHZD nWE 'HZ' tXnBRQH tXnBRQS XnBREQ tXnBRQL XnBACK tXnBACKD tXnBACKD Figure 27-21 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2) 27-23
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD tSRD tSRD nGCSx nSRAS tSCD nSCAS nBEx '1' tSWD tSWD nWE DATA 'HZ' Figure 27-22 SDRAM MRS Timing Diagram 27-24
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSRD tSRD tSCSD nGCSx nSRAS Trp Trcd tSCD nSCAS tSBED nBEx Tcl tSWD nWE tSDS DATA tSDH Figure 27-23 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) 27-25
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSRD tSRD tSCSD nGCSx nSRAS Trp Trcd tSCD nSCAS tSBED nBEx Tcl tSWD nWE tSDS DATA tSDH Figure 27-24 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3) 27-26
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD tSRD tSRD nGCSx nSRAS '1' Trp Trc tSCD nSCAS nBEx '1' tSWD nWE DATA NOTE: 'HZ' Before executing an auto/self refresh command, all the banks must be in idle state.
S3C2440A RISC MICROPROCESSOR tSWD tSRD DATA nWE nBEx nSCAS nSRAS nGCSx A10/AP ADDR/BA SCKE SCLK '1' tSAD tSAD tSCSD Trp Trcd tSCD tSBED Tcl Tcl tSDS tSDH Tcl ELECTRICAL DATA Figure 27-26 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2) 27-28
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA SCLK tCKED tCKED SCKE tSAD tSAD ADDR/BA tSAD A10/AP tSCSD tSCSD '1' nGCSx tSRD tSRD nSRAS '1' '1' Trc Trp tSCD '1' nSCAS nBEx '1' '1' tSWD nWE DATA '1' 'HZ' NOTE: 'HZ' Before executing an auto/self refresh command, all the banks must be in idle state.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD tSAD A10/AP tSCSD tSCSD tSRD tSRD tSCSD nGCSx nSRAS Trp Trcd tSCD nSCAS tSBED nBEx tSWD tSWD nWE tSDD DATA tSDD Figure 27-28.
ELECTRICAL DATA tSDD tSWD tSRD DATA nWE nBEx nSCAS nSRAS nGCSx A10/AP ADDR/BA SCKE SCLK '1' tSAD tSAD tSCSD Trp Trcd tSCD tSBED tSDD S3C2440A RISC MICROPROCESSOR Figure 27-29.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR XSCLK tXRS XnXDREQ tXRS tXAD tCADH XnXDACK Min. 3SCLK Read Write tCADL Figure 27-30. External DMA Timing Diagram (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvspw Tvfpd Tvbpd VDEN HSYNC Tl2csetup Tvclkh Tvclk VCLK Tvclkl Tvdhold VD Tvdsetup Tve2hold VDEN Tle2chold LEND Tlewidth Figure 27-31.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA IISSCLK tLRCK IISLRCK (out) tSDO IISLRCK (out) tSDIS tSDIH IISSDI (in) Figure 27-32. IIS Interface Timing Diagram fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSDAS tSDAH tSTARTS IICSDA Figure 27-33.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR SDCLK tSDCD SDCMD (out) tSDCS tSDCH SDCMD (in) tSDDD SDDATA[3:0] (out) tSDDS tSDDH SDDATA[3:0] (in) Figure 27-34. SD/MMC Interface Timing Diagram SPICLK tSPIMOD SPIMOSI (MO) tSPISIS tSPISIH SPIMOSI (SI) tSPISOD SPIMISO (SO) tSPIMIS tSPIMIH SPIMISO (MI) Figure 27-35.
S3C2440A RISC MICROPROCESSOR TACLS TWRPH0 ELECTRICAL DATA TWRPH1 TACLS HCLK TWRPH1 HCLK tCLED tCLED tALED CLE tALED ALE tWED tWED tWED nFWE tWED nFWE tWDS DATA[7:0] TWRPH0 tWDS tWDH DATA[7:0] COMMAND tWDH ADDRESS Figure 27-36. NAND Flash Address/Command Timing Diagram TWRPH0 TWRPH1 TWRPH0 HCLK HCLK tWED tWED tWED nFWE tWED nFRE tWDS DATA[7:0] TWRPH1 tWDH WDATA tRDS DATA[7:0] RDATA tRDH Figure 27-37.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27-7 Clock Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VDDMOP = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit Crystal clock input frequency fXTAL 12 – 20 MHz Crystal clock input cycle time tXTALCYC 50 – 83.3 ns External clock input frequency fEXT – – 66 MHz External clock input cycle time tEXTCYC 15.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA Table 27-8 ROM/SRAM Bus Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VDDMOP = 3.3V ± 0.3V / 3.0V ± 0.3V / 2.5V ± 0.2V / 1.8V ± 0.1V) Symbol Min (VDDMOP = 3.3V/3.0V/2.5V/1.8V) Typ Max (VDDMOP = 3.3V/3.0V/2.5V/1.8V) Unit ROM/SRAM Address Delay tRAD 2/2/2/3 – 6/6/7/8 ns ROM/SRAM Chip Select Delay tRCD 2/2/3/3 – 6/6/6/7 ns ROM/SRAM Output Enable Delay tROD 2/2/2/3 – 5/5/5/6 ns ROM/SRAM Read Data Setup Time.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27-10 External Bus Request Timing Constants (VDD = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit External Bus Request Setup Time tXnBRQS 2 – 4 ns External Bus Request Hold Time tXnBRQH 0 – 1 ns External Bus Ack Delay tXnBACKD 4 – 10 ns tHZD 2 – 6 ns HZ Delay Table 27-11 DMA Controller Module Signal Timing Constants (VDD = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA Table 27-12 TFT LCD Controller Module Signal Timing Constants (VDD = 1.2 V ± 0.05 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Units Vertical Sync Pulse Width Tvspw VSPW + 1 – – Phclk (note1) Vertical Back Porch Delay Tvbpd VBPD+1 – – Phclk Vertical Front Porch Delay Tvfpd VFPD+1 – – Phclk VCLK Pulse Width Tvclk 1 – – Pvclk (note2) VCLK Pulse Width High Tvclkh 0.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27-14 IIC BUS Controller Module Signal Timing (VDD = 1.2 V ± 0.05 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit fSCL – – std. 100 fast 400 KHz SCL High Level Pulse Width tSCLHIGH std. 4.0 fast 0.6 – – µs SCL Low Level Pulse Width tSCLLOW std. 4.7 fast 1.3 – – µs tBUF std. 4.7 fast 1.3 – – µs tSTARTS std. 4.0 fast 0.6 – – µs SDA Hold Time tSDAH std. 0 fast 0 – std. – fast 0.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA Table 27-16 SPI Interface Transmit/Receive Timing Constants (VDD = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V) Parameter Symbol Min Typ.
ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27-18 USB Full Speed Output Buffer Electrical Characteristics (VDD = 1.2 V ± 0.05 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V) Parameter Symbol Condition Min Max Unit Rise Time TR CL = 50pF 4.0 20 Fall Time TF CL = 50pF 4.0 20 Rise/Fall Time Matching Trfm (TR / TF ) 90 111.1 % Output Signal Crossover Voltage Vcrs 1.3 2.
