Laptop User Manual
S3C2440A RISC MICROPROCESSOR     MEMORY CONTROLLER 
DEC.13, 2002 
  5-13 
BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) 
Register Address R/W  Description  Reset Value 
BWSCON  0x48000000  R/W  Bus width & wait status control register  0x000000 
BWSCON Bit  Description  Initial state 
ST7  [31]  Determines SRAM for using UB/LB for bank 7. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 
1 = Using UB/LB (The pins are dedicated nBE[3:0]) 
0 
WS7  [30]  Determines WAIT status for bank 7. 
0 = WAIT disable 1 = WAIT enable 
0 
DW7  [29:28] Determines data bus width for bank 7. 
00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 
0 
ST6  [27]  Determines SRAM for using UB/LB for bank 6. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0 ) 
1 = Using UB/LB (The pins are dedicated nBE[3:0]) 
0 
WS6  [26]  Determines WAIT status for bank 6. 
0 = WAIT disable, 1 = WAIT enable 
0 
DW6  [25:24] Determines data bus width for bank 6. 
00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 
0 
ST5  [23]  Determines SRAM for using UB/LB for bank 5. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 
1 = Using UB/LB (The pins are dedicated nBE[3:0]) 
0 
WS5  [22]  Determines WAIT status for bank 5. 
0 = WAIT disable, 1 = WAIT enable 
0 
DW5  [21:20] Determines data bus width for bank 5. 
00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 
0 
ST4  [19]  Determines SRAM for using UB/LB for bank 4. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 
1 = Using UB/LB (The pins are dedicated nBE[3:0]) 
0 
WS4  [18]  Determines WAIT status for bank 4. 
0 = WAIT disable 1 = WAIT enable 
0 
DW4  [17:16] Determine data bus width for bank 4. 
00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 
0 
ST3  [15]  Determines SRAM for using UB/LB for bank 3. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 
1 = Using UB/LB (The pins are dedicated nBE[3:0]) 
0 
WS3  [14]  Determines WAIT status for bank 3. 
0 = WAIT disable 1 = WAIT enable 
0 
DW3  [13:12] Determines data bus width for bank 3. 
00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 
0 
ST2  [11]  Determines SRAM for using UB/LB for bank 2. 
0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 
1 = Using UB/LB (The pins are dedicated nBE[3:0].) 
0 










