Laptop User Manual

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR

14-18

INTERRUPT SUB MASK (INTSUBMSK) REGISTER

This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt

request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the

corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be

serviced.

INTSUBMSK 0X4A00001C R/W Determine which interrupt source is masked. The

masked interrupt source will not be serviced.

0 = Interrupt service is available.

1 = Interrupt service is masked.

0xFFFF

INTSUBMSK Bit Description Initial State

Reserved [31:15] Not used 0

INT_AC97 [14] 0 = Service available, 1 = Masked 1

INT_WDT [13] 0 = Service available, 1 = Masked 1

INT_CAM_P [12] 0 = Service available, 1 = Masked 1

INT_CAM_C [11] 0 = Service available, 1 = Masked 1

INT_ADC_S [10] 0 = Service available, 1 = Masked 1

INT_TC [9] 0 = Service available, 1 = Masked 1

INT_ERR2 [8] 0 = Service available, 1 = Masked 1

INT_TXD2 [7] 0 = Service available, 1 = Masked 1

INT_RXD2 [6] 0 = Service available, 1 = Masked 1

INT_ERR1 [5] 0 = Service available, 1 = Masked 1

INT_TXD1 [4] 0 = Service available, 1 = Masked 1

INT_RXD1 [3] 0 = Service available, 1 = Masked 1

INT_ERR0 [2] 0 = Service available, 1 = Masked 1

INT_TXD0 [1] 0 = Service available, 1 = Masked 1

INT_RXD0 [0] 0 = Service available, 1 = Masked 1