Laptop User Manual

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR

20-6

READ-WRITE OPERATION

In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS)

released after it is written. The S3C2440A should hold the interrupt to identify the completion of current data

transfer. After the CPU receives the interrupt request, it should write a new data into the IICDS register, again.

In Receive mode, when data is received, the IIC-bus interface will wait until IICDS register is read. Before the new

data is read out, the SCL line will be held low and then released after it is read. The S3C2440A should hold the

interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should

read the data from the IICDS register.

BUS ARBITRATION PROCEDURES

Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a

SDA High level detects the other master with a SDA active Low level, it will not initiate a data transfer because the

current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line

turns High.

However, when the masters simultaneously lower the SDA line, each master should evaluate whether the

mastership is allocated itself or not. For the purpose of evaluation is that each master should detect the address

bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because

the SDA line is likely to get Low rather than to keep High. Assume that one master generates a Low as first address

bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because the

Low status is superior to the High status in power. When this happens, Low (as the first bit of address) generating

master will get the mastership while High (as the first bit of address) generating master should withdraw the

mastership. If both masters generate Low as the first bit of address, there should be arbitration for the second

address bit, again. This arbitration will continue to the end of last address bit.

ABORT CONDITIONS

If a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the SDA line

High. In this case, the master should generate a Stop condition and to abort the transfer.

If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by

canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should

then release the SDA to allow a master to generate a Stop condition.

CONFIGURING IIC-BUS

To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON

interface address has an unknown value.)