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USER'S MANUAL

S3F84A5

8-Bit CMOS Microcontrollers

July 2009

REV 1.10

Summary of content (379 pages)

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Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
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Preface The S3F84A5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3F84A5 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure.
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NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, SSCR PRODUCT NAME: S3F84A5 8-bit CMOS Microcontroller DOCUMENT NAME: S3F84A5 User's Manual, Revision 1.10 DOCUMENT NUMBER: S3-F84A5-052009 EFFECTIVE DATE: July 2009 SUMMARY: As a result of additional product testing and evaluation, some specifications published in the S3F84A5 User's Manual, Revision 1.0, have been changed.
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REVISION HISTORY Revision Date Remark 0.00 Dec, 2007 Preliminary Spec for internal release only. 0.09 July, 2008 First edition. 0.10 Oct, 2008 Ver0.10. 1.00 May, 2009 Ver1.00. 1.10 July, 2009 Ver1.10 S3F84A5_UM_REV1.
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REVISION DESCRIPTIONS (REV 0.10) Chapter Chapter Name Page Subjects (Major changes comparing with last version) 1-2 Revised LVR level to 2.3V/3.0V/3.6V/3.9V. 1-2 Deleted 28-SSOP package. 2. Address 2-3 Revised LVR level to 2.3V/3.0V/3.6V/3.9V. 16. Low Voltage Reset 16-1 Revised LVR level to 2.3V/3.0V/3.6V/3.9V. 1. Overview 17. Embedded Flash Memory Interface 17-3 18. Electrical Data 18-7 18-10 18-12 19. Mechanical Data 19-2 21. Development vi - Revised LVR level to 2.3V/3.0V/3.6V/3.9V.
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REVISION DESCRIPTIONS (Rev 1.00) Chapter Chapter Name Page 1. Overview 1-2 Revised LVR level to 2.3V/3.0V/3.9V. 1-2 1-2 Revised Operating Voltage Range to 2.0V to 5.5V @ 0.4-4MHz(LVR disable), LVR to 5.5V @ 0.4-4MHz(LVR enable). Added 32-ELP package. 1-5 Added 32-ELP pin assignment. 1-6,1-7 Revised pin description. 2. Address 2-3 Revised LVR level to 2.3V/3.0V/3.9V. 16. Low Voltage Reset 16-1 Revised LVR level to 2.3V/3.0V/3.9V. 17. Embedded Flash 17-3 Revised LVR level to 2.3V/3.0V/3.9V.
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REVISION DESCRIPTIONS (Rev 1.10) Chapter Chapter Name Page 1. Overview 1-2 Added 28-SSOP package. 19. Mechanical Data 19-2 Added 28-pin SSOP package dimensions. viii Subjects (Major changes comparing with last version) S3F84A5_UM_REV1.
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Table of Contents Part I — Programming Model Chapter 1 Product Overview S3F8-Series Microcontrollers........................................................................................................................1-1 S3F84A5 Microcontroller...............................................................................................................................1-1 Features ...........................................................................................................................
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Table of Contents (Continued) Chapter 4 Control Registers Overview ....................................................................................................................................................... 4-1 Chapter 5 Interrupt Structure Overview ....................................................................................................................................................... 5-1 Interrupt Types .........................................................................
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Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview........................................................................................................................................................7-1 Main Oscillator Logic..................................................................................................................................7-1 Clock Status During Power-Down Modes.......................................................................
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Table of Contents (Continued) Chapter 11 8-Bit Timer A/B 8-Bit Timer A................................................................................................................................................. 11-1 Overview................................................................................................................................................... 11-1 Function Description............................................................................................................
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Table of Contents (Continued) Chapter 15 10-bit A/D Converter Overview........................................................................................................................................................15-1 Function Description......................................................................................................................................15-1 Conversion Timing ..........................................................................................................
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Table of Contents (Continued) Chapter 19 Mechanical Data Overview........................................................................................................................................................ 19-1 Chapter 20 S3F84A5 Flash MCU Overview ....................................................................................................................................................... 20-1 On Board Writing ........................................................................
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List of Figures Figure Number Title Page Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 S3F84A5 Block Diagram ............................................................................................1-3 S3F84A5 Pin Assignment (28-SOP, 28-SSOP) .........................................................1-4 S3F84A5 Pin Assignment (32-ELP) ...........................................................................1-5 Pin Circuit Type B (nRESET) .........................
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List of Figures (Continued) Figure Number Title Page Number 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 Register Addressing................................................................................................... 3-2 Working Register Addressing .................................................................................... 3-2 Indirect Register Addressing to Register File ............................................................
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List of Figures (Continued) Figure Number Title Page Number 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 Port 0 Control Register (P0CON) ...............................................................................9-4 Port 1 High-Byte Control Register (P1CONH) ...........................................................9-6 Port 1 Low-Byte Control Register (P1CONL).............................................................9-7 Port 1 Interrupt Control Register (P1INT)..................................
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List of Figures (Concluded) Figure Number Title Page Number 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 UART Control Register (UARTCON)......................................................................... 14-2 UART Interrupt Pending Register (UARTPND) ......................................................... 14-3 UART Data Register (UDATA) .................................................................................. 14-4 UART Baud Rate Data Register (BRDATA)..............................
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List of Figures (Concluded) Figure Number Title Page Number 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 Input Timing for External Interrupts ............................................................................18-5 Input Timing for RESET..............................................................................................18-5 Operating Voltage Range (S3F84A5) ........................................................................18-6 Stop Mode Release Timing When Initiated by a RESET .......
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List of Tables Table Number Title Page Number 1-1 1-2 Pin Descriptions of 28-SOP, 28-SSOP (32-ELP).......................................................1-6 Descriptions of Pins Used to Read/Write the Flash ROM..........................................1-8 2-1 S3F84A5 Register Type Summary.............................................................................2-4 4-1 4-2 4-3 Set 1 Registers ..........................................................................................................
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List of Tables Table Number Title Page Number 20-1 Descriptions of Pins Used to Read/Write the Flash ROM ......................................... 20-3 21-1 21-2 21-3 21-4 21-5 21-6 Components of TB84A5............................................................................................. 21-4 Power Selection Settings for TB84A5........................................................................ 21-4 The SMDS2+ Tool Selection Setting ..........................................................
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List of Programming Tips Description Chapter 2: Page Number Address Spaces Using the Page Pointer for RAM clear ...........................................................................................................2-7 Setting the Register Pointers .........................................................................................................................2-11 Using the RPs to Calculate the Sum of a Series of Registers.......................................................................
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List of Register Descriptions Register Identifier ADCONH ADCONL BTCON CLKCON FLAGS FMCON FMUSR FMSECH FMSECL IMR IPH IPL IPR IRQ P0CON P1CONH P1CONL P1INT P2CONH P2CONL P3CONH P3CONL P3INT P3PND P3PUR PP PWMCON P2PWMOUT PWMINT RESETID RP0 RP1 SPH SPL STPCON SYM T0CON TACON TBCON TINTPND UARTCON UARTPND Full Register Name Page Number A/D Converter Control Register (High Byte) .............................................................. 4-5 A/D Converter Control Register (Low Byte) ......................
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List of Instruction Descriptions Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LD LDB Full Register Name Page Number Add with Carry............................................................................................................ 6-14 Add .........................................................................................................................
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List of Instruction Descriptions (Continued) Instruction Mnemonic LDC/LDE LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR xxviii Full Register Name Page Number Load Memory..............................................................................................................6-52 Load Memory..................................................................
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S3F84A5_UM_REV1.10 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3F8-SERIES MICROCONTROLLERS Samsung's SAM8RC family of 8-bit single-chip CMOS microcontrollers offer a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. An address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW BLOCK DIAGRAM (ADC0-7) A/D XIN XOUT nRESET Port 0 P0.0P0.2 Port 1 P1.0P1.7 OSC/nRESET I/O Port and Interrupt Control 8-Bit Basic Timer TAOUT TACK TACAP 8-Bit Timer /Counter A T0OUT T0CK T0CAP 16-bit Timer /Counter 0 TBOUT 8-Bit Timer /Counter B SAM8RC CPU 16-Kbyte ROM 400-Byte RAM Port 2 P2.0P2.7 Port 3 P3.0P3.4 UART P2.7/PWM3A P2.4/PWM2A P2.1/PWM1A PWM RXD TXD P2.6/PWM3B P2.3/PWM2B P2.0/PWM1B Figure 1-1.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 PIN ASSIGNMENT VSS XOUT/P3.3 XIN/P3.4 (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S3F84A5 (Top View) 28-SOP 28-SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P3.2/INT4 (SCLK) P3.1/INT3 (SDAT) P3.0/INT2 P2.7/T0OUT/PWM3A P2.6/T0CAP/PWM3B P2.5/TBOUT P2.4/T0CK/PWM2A P2.3/PWM2B P2.2/TACAP P2.1/TACK/PWM1A P2.0/TAOUT/PWM1B P1.7/ADC7 P1.6/ADC6 Figure 1-2.
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P1.7/ADC7 P1.6/ADC6 P1.5/ADC5 20 19 18 P1.4/ADC4 P2.0/TAOUT/PWM1B 21 17 P2.1/TACK/PWM1A 22 25 P2.2/TACAP 24 PWM2B/P2.3 23 PRODUCT OVERVIEW NC S3F84A5_UM_REV1.10 16 NC 12 P1.0/ADC0/INT0 INT2/P3.0 30 32-ELP 11 AVREF NC 31 10 P0.2/nRESET NC 32 9 RxD/P0.0 (Top View) 8 29 (Vpp)TEST PWM3A/T0OUT/P2.7 7 P1.1/ADC1/INT1 6 13 Xin/P3.4 S3F84A5 5 28 Xout/P3.3 PWM3B/T0CAP/P2.6 4 P1.2/ADC2 VSS 14 3 27 VDD TBOUT/P2.5 2 P1.3/ADC3 (SCLK)INT4/P3.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 PIN DESCRIPTIONS Table 1-1. Pin Descriptions of 28-SOP, 28-SSOP (32-ELP) Pin Names Pin Type Pin Description Pin No. Shared Functions 5-7 (8-10) RxD TxD RESETB P0.0 P0.1 P0.2 I/O P1.0 − P1.1 P1.2 − P1.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW Table 1-1. Pin Descriptions of 28-SOP, 28-SSOP (32-ELP) (Continued) Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions INT0 − INT1 INT2 − INT4 I/O Input pins for external interrupt. Alternatively used as general-purpose input/output port 1 and port 3. D-3 D-2 9-10(12-13) 25-27 (30,1-2) P1.0−P1.1 P3.0−P3.2 ADC0 − ADC1 ADC2 − ADC7 I/O Analog input pins for A/D converter module. Alternative used as general-purpose input/output port 1.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 Table 1-2. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O P3.1 SDAT 26 (28-pin) 1 (32-pin) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as an Input or push-pull output port. P3.2 SCLK 27 (28-pin) 2 (32-pin) I/O Serial clock pin. Input only pin.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW PIN CIRCUITS VDD P-Channel Data IN Out N-Channel Output Disable Figure 1-4. Pin Circuit Type B (nRESET) Figure 1-5. PAD Driver A VDD Open-Drain Pull-up Enable VDD P-Channel Data Out Output Disable N-Channel Port Data output Alternative output M U X PAD Driver A I/O Output Disable Port Data IN Alternative Input Figure 1-6. PAD Driver B Figure 1-7.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 V DD Pull-up Enable Open-Drain Port Data output Output Disable Port Data IN Ext.INT Noise Filter Figure 1-8.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW V DD Pull-up Enable Port Data output PAD Driver A I/O Output Disable Port Data IN Ext.INT Noise Filter Analog Input Figure 1-9.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 V DD P2PWMOUT Register PWM output Port Data output M U X Alternative output M U X Pull-up Enable Open-Drain Data Output Disable PAD Driver B I/O P2CONH/L Register Port Data IN Alternative Input Figure 1-10. Pin Circuit Type D-4 V DD P2PWMOUT Register PWM output Port Data output M U X Alternative output M U X Pull-up Enable Open-Drain Data Output Disable P2CONH/L Register Port Data IN Figure 1-11.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW V DD P2PWMOUT Register Pull-up Enable PWM output Port Data output M U X Alternative output M U X P2CONH/L Register Data Output Disable PAD Driver B I/O Port Data IN Figure 1-12.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 V DD Pull-up Enable Open-Drain Port Data output Output Disable PAD Driver B I/O Port Data IN Alternative Input Figure 1-13. Pin Circuit Type E VDD Pull-up Enable Port Data output PAD Driver A Output Disable Port Data IN Analog Input Figure 1-14.
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S3F84A5_UM_REV1.10 PRODUCT OVERVIEW VDD Pull-up Enable Open-Drain PAD Driver B Port Data output Output Disable Smart option Xout Xin nRESET I/O Port Data IN MUX Figure 1-15. Pin Circuit Type E-2 V DD Pull-up Enable Port Data output Alternative output M U X Data PAD Driver A I/O Output Disable Port Data IN Figure 1-16.
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PRODUCT OVERVIEW S3F84A5_UM_REV1.10 V DD Pull-up Enable Port Data output Output Disable PAD Driver A Port Data IN Alternative Input Figure 1-17.
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S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F84A5 microcontroller has two kinds of address space: • Internal program memory (ROM) • Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3F84A5 have 16-Kbytes of on-chip program memory, which is configured as the Internal ROM mode, all of the 16-Kbyte internal program memory is used.
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ADDRESS SPACES S3F84A5_UM_REV1.10 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3F84A5 have 16Kbytes of internal multi time programmable (MTP) program memory (see Figure 2-1). The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (except 3CH, 3DH, 3EH, 3FH) in this address range can be used as normal program memory.
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S3F84A5_UM_REV1.10 ADDRESS SPACES Smart Option Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from 003EH to 003FH. 003CH and 003DH are not used in S3F84A5. The default value of ROM is FFH. Figure 2-2.
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ADDRESS SPACES S3F84A5_UM_REV1.10 REGISTER ARCHITECTURE In the S3F84A5 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3F84A5 the total number of addressable 8-bit registers is 464.
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S3F84A5_UM_REV1.
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ADDRESS SPACES S3F84A5_UM_REV1.10 REGISTER PAGE POINTER (PP) The S3F8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH).
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S3F84A5_UM_REV1.
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ADDRESS SPACES S3F84A5_UM_REV1.10 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing.
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S3F84A5_UM_REV1.10 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3F84A5's a 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages, you must set the register page pointer (PP) to the appropriate source and destination values.
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ADDRESS SPACES S3F84A5_UM_REV1.10 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
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S3F84A5_UM_REV1.10 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, RP# point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-7 and 2-8).
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ADDRESS SPACES S3F84A5_UM_REV1.10 F7H (R7) 8-Byte Slice F0H (R0) Register File Contains 32 8-Byte Slices 1 1 1 1 0 X X X 16-byte Noncontiguous working register block RP0 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R8) RP1 Figure 2-8. Non-Contiguous 16-Byte Working Register Block PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer.
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S3F84A5_UM_REV1.10 ADDRESS SPACES REGISTER ADDRESSING The S3F8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
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ADDRESS SPACES S3F84A5_UM_REV1.10 Special-Purpose Registers Bank 1 General-Purpose Register Bank 0 FFH FFH Control Registers Set 2 E0H System Registers D0H CFH C0H BFH C0H RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the 32 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area).
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S3F84A5_UM_REV1.10 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
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ADDRESS SPACES S3F84A5_UM_REV1.10 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.
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S3F84A5_UM_REV1.10 ADDRESS SPACES RP0 RP1 Selects RP0 or RP1 Address OPCODE 4-bit address provides three low-order bits Register pointer provides five high-order bits Together they create an 8-bit register address Figure 2-12. 4-Bit Working Register Addressing RP0 0 1 1 1 0 RP1 0 0 0 0 1 1 1 1 0 0 0 Selects RP0 0 1 1 1 0 1 1 0 Register address (76H) R6 OPCODE 0 1 1 0 1 1 1 0 Instruction 'INC R6' Figure 2-13.
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ADDRESS SPACES S3F84A5_UM_REV1.10 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.
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S3F84A5_UM_REV1.10 ADDRESS SPACES RP0 0 1 1 0 0 RP1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Selects RP1 R11 1 1 0 0 1 0 1 1 8-bit address form instruction 'LD R11, R2' Register address (0ABH) Specifies working register addressing Figure 2-15.
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ADDRESS SPACES S3F84A5_UM_REV1.10 SYSTEM AND USER STACK The S3F8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3F84A5 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack.
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S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM8RCinstructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.
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ADDRESSING MODES S3F84A5_UM_REV1.10 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
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S3F84A5_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register.
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ADDRESSING MODES S3F84A5_UM_REV1.10 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE Register Pair Points to Register Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in instruction OPERAND Figure 3-4.
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S3F84A5_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Program Memory 4-bit Working Register Address dst src OPCODE ~ ~ 3 LSBs Point to the Working Register (1 of 8) ADDRESS ~ Sample Instruction: OR R3, @R6 Value used in Instruction Selected RP points to start fo working register block ~ OPERAND Figure 3-5.
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ADDRESSING MODES S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using indexed addressing mode.
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ADDRESSING MODES S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.
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ADDRESSING MODES S3F84A5_UM_REV1.10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
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S3F84A5_UM_REV1.10 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11.
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ADDRESSING MODES S3F84A5_UM_REV1.10 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode.
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S3F84A5_UM_REV1.10 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.
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ADDRESSING MODES S3F84A5_UM_REV1.10 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14.
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S3F84A5_UM_REV1.10 4 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3F84A5 register file are listed in Table 4-1, 4-2 and 4-3.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 Table 4-2.
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S3F84A5_UM_REV1.10 CONTROL REGISTER Table 4-3.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 Name of individual bit or related bits Bit number(s) that is/are appended to the register name for bit addressing Register ID Register address (hexadecimal) Register name FLAGS - System Flags Register Bit Identifier RESET Value Read/Write .7 .6 .5 D5H .7 .6 .5 .4 .3 .2 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER ADCONH — A/D Converter Control Register (High Byte) FBH Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for the S3F84A5 .6-.4 A/D Input Pin Selection Bits .3 .2-.1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 ADCONL — A/D Converter Control Register (Low Byte) F3H Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 – – 0 0 Read/Write – R/W R/W R/W – – R/W R/W .7 Not used for the S3F84A5 (reserved) .6-.
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S3F84A5_UM_REV1.10 CONTROL REGISTER BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7–.4 Watchdog Timer Function Enable Bit 1 0 1 0 Others .3–.2 .1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – 0 0 – – – Read/Write – – – R/W R/W – – – .7-.5 Not used for the S3F84A5 .4-.3 CPU Clock (System Clock) Selection Bits (note) .2-.0 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx/1 (non-divided) Not used for the S3F84A5 NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock.
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S3F84A5_UM_REV1.10 CONTROL REGISTER FLAGS — System Flags Register Bit Identifier .7 .6 D5H .5 Reset Value Read/Write Addressing Mode x x x R/W R/W R/W Register addressing mode only .7 Carry Flag (C) .6 .5 .4 .3 .2 .1 .0 Set 1 .4 .3 .2 .1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 FMCON — Flash Memory Control Register F4H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 – – – 0 Read/Write R/W R/W R/W R/W – – – R/W Addressing Mode Register addressing mode only .7–.4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector erase mode 0 1 1 0 Hard lock mode Other values Not available .3–.1 Not used for the S3F84A5 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER FMSECH — Flash Memory Sector Address Register (High Byte) F6H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 FMUSR — Flash Memory User Programming Enable Register F5H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.
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S3F84A5_UM_REV1.10 CONTROL REGISTER IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit .6 .5 .4 .3 .2 .1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).
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S3F84A5_UM_REV1.10 CONTROL REGISTER IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C (note) .6 .5 .3 .2 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit .6 .5 .4 .3 .2 .1 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER P0CON — Port 0 Control Register E6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W .7-.6 Not used for S3F84A5 .5-.4 P0.2 .3–.2 .1-.0 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output 1 1 Open-drain Output P0.1/TxD 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output 1 1 Alternative function, TxD output P0.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 P1CONH — Port 1 Control Register (High Byte) E8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-18 P1.7/ADC7 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output 1 1 Alternative function; ADC7 input P1.
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S3F84A5_UM_REV1.10 CONTROL REGISTER P1CONL — Port 1 Control Register (Low Byte) E9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 P1.3/ADC3 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output 1 1 Alternative function; ADC3 input P1.
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CONTROL REGISTERS P1INT — S3F84A5_UM_REV1.10 Port 1 Interrupt Control Register E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W .7-.6 Not used for S3F84A5 .5-.4 P1.1/ INT1 Interrupt Enable/Disable Selection Bits .3-.2 .1 .0 4-20 0 X Interrupt Disable 1 0 Interrupt Enable; falling edge 1 1 Interrupt Enable; rising edge P1.
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S3F84A5_UM_REV1.10 CONTROL REGISTER P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7–.6 .5-.4 .3–.2 .1–.0 P2.7/T0OUT/PWM3A 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output or PWM3A output 1 1 Alternative function; T0OUT signal output P2.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-22 P2.3/PWM2B 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output or PWM2B output 1 1 Open-drain output P2.
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S3F84A5_UM_REV1.10 CONTROL REGISTER P3CONH — Port 3 Control Register (High Byte) ECH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.2 Not used for S3F84A5 .1–.0 P3.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 P3CONL — Port 3 Control Register (Low Byte) EDH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7–.6 .5–.4 .3–.2 .1–.0 4-24 P3.3 0 0 Input mode 0 1 Input mode with pull-up 1 0 Push-pull output 1 1 Open-drain output P3.
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S3F84A5_UM_REV1.10 CONTROL REGISTER P3INT — Port 3 Interrupt Control Register EEH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7–.3 Not used for S3F84A5 .2 P3.2/INT4, Falling & Rising Edge Interrupt Enable/Disable Selection Bit .1 .0 0 INT4 interrupt disable 1 INT4 interrupt enable P3.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 P3PND — Port 3 Interrupt Pending Register EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7–.3 Not used for S3F84A5 .2 Port 3.2/INT4, External Interrupt Pending Bit .1 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER P3PUR — Port 3 Pull-up Resistor Control Register F0H Set1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – 0 0 0 Read/Write – – – – – R/W R/W R/W Addressing Mode Register addressing mode only .7–.3 Not used for S3F84A5 .2 P3.2 Pull-up Resistor Enable/Disable .1 .0 0 Pull-up resistor disable 1 Pull-up resistor enable P3.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 PP — Register Page Pointer DFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7–.4 Destination Register Page Selection Bits 0 0 0 0 Destination: page 0 0 0 0 1 Destination: page 1 Other values .3–.
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S3F84A5_UM_REV1.10 PWMCON — CONTROL REGISTER PWM Control Register F1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 – 0 0 0 0 0 R/W R/W – R/W R/W R/W R/W R/W Read/Write .7–.6 PWM Input Clock Selection Bit 0 0 fosc/256 0 1 fosc/64 1 0 fosc/8 1 1 fosc/1 .5 Not used for S3F84A5 .4 PWM(PWM1A~PWM3A, PWM1B~PWM3B) Waveform Mode Selection bit .3 .2 .1 .
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CONTROL REGISTERS P2PWMOUT— S3F84A5_UM_REV1.10 Port 2 PWM Output Control Register F2H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 – 0 0 – 0 0 R/W R/W – R/W R/W – R/W R/W Read/Write .7 .6 P2.7/PWM3A pin PWM Output Selection bit 0 Normal I/O port output pin (P2.7) 1 PWM3A output pin P2.6/PWM3B pin PWM Output Selection bit 0 Normal I/O port output pin (P2.6) 1 PWM3B output pin .5 Not used for S3F84A5 .4 P2.
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S3F84A5_UM_REV1.10 PWMINT— CONTROL REGISTER PWM Interrupt Control Register F4H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value R/W 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W .7 .6–.5 .4–.3 .2 .1 .
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CONTROL REGISTERS RESETID— S3F84A5_UM_REV1.10 Reset Source Indicating Register F3H Set 1, Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Read/Write – – – R/W – R/W R/W – .2 .1 .0 Addressing Mode Register addressing mode only .7 – .5 Not used for S3F84A5 .4 nReset pin Indicating Bit 0 Reset is not generated by nReset pin (when read) 1 Reset is generated by nReset pin (when read) .3 Not used for S3F84A5 .2 WDT Reset Indicating Bit .1 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER RP0 — Register Pointer 0 D6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 1 1 0 0 0 – – – R/W R/W R/W R/W R/W – – – Read/Write Addressing Mode Register addressing only .7–.3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 SPH — Stack Pointer (High Byte) D8H Set 1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8). The lower byte of the stack pointer value is located in register SPL (D9H).
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S3F84A5_UM_REV1.10 CONTROL REGISTER STPCON — Stop Control Register D1H Set 1, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7–.0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE: Before executing the STOP instruction, you must set this STPCON register as “10100101b”. Otherwise the STOP instruction will not be executed.
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CONTROL REGISTERS S3F84A5_UM_REV1.10 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W .7 Tri-state External Interface Control Bit (1) 0 Normal operation (disable tri-state operation) 1 Set external interface lines to high impedance (enable tri-state operation) .6–.5 Not used for the S3F84A5 .4–.2 Fast Interrupt Level Selection Bits (2) .1 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER T0CON — Timer 0 Control Register E8H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7-.5 Timer 0 Input Clock Selection Bits .4-.3 .2 .1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 TACON — Timer A Control Register E4H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3 .2 .1 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER TBCON — Timer B Control Register E5H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.5 .4 .3 .2 .1 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 TINTPND — Timer Interrupt Pending Register F1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 – – 0 0 0 0 R/W R/W – – R/W R/W R/W R/W Read/Write .7 Timer 0 Overflow Interrupt Pending Bit 0 No interrupt pending (Clear pending bit when write) 1 .6 Interrupt pending Timer 0 Match/Capture Interrupt Pending Bit 0 No interrupt pending (Clear pending bit when write) 1 Interrupt pending .5-.4 Not used for S3F84A5 .
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S3F84A5_UM_REV1.10 CONTROL REGISTER UARTCON — UART Control Register F5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Addressing Mode Register addressing mode only .7–.6 Operating mode and baud rate selection bits .5 .
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CONTROL REGISTERS S3F84A5_UM_REV1.10 UARTPND — UART Interrupt Pending Register F6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.3 Not used for the S3F84A5 .1 UART receive interrupt pending flag .0 0 Not pending 0 Clear pending bit (when write) 1 Interrupt pending UART transmit interrupt pending flag 0 Not pending 0 Clear pending bit (when write) 1 Interrupt pending NOTES: 1.
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S3F84A5_UM_REV1.10 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 INTERRUPT TYPES The three components of the S3F8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE S3F84A5 INTERRUPT STRUCTURE The S3F84A5 microcontroller supports 17 interrupt sources. Every interrupt source has a corresponding interrupt address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 Levels Vectors RESET 100H Sources Reset/Clear Basic timer overflow H/W D0H Timer A overflow H/W,S/W D2H Timer A match/capture S/W D4H Timer B overflow H/W,S/W D6H Timer B match S/W D8H A/D Conv. Complete interrupt S/W DEH PWM 8-bit Counter Overflow H/W,S/W E0H PWMA match interrupt S/W F0H PWMB match interrupt S/W E2H Timer 0 overflow H/W,S/W E4H Timer 0 match/capture S/W E6H P1.0 external interrupt(INT0) S/W E8H P1.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE Interrupt Vector Addresses All interrupt vector addresses for the S3F84A5 interrupt structure is stored in the vector address area of the first 256 bytes of the program memory (ROM). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses. The default program reset address in the ROM is 0100H.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 Enable/Disable Interrupt Instructions (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-2). Table 5-2.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set1), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is undetermined. The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set1) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set1, Bank0), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 Interrupt Priority Register (IPR) FFH, Set1, Bank0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set1), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the source's interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6.
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.10 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4.
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S3F84A5_UM_REV1.10 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: — The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and — When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime").
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INTERRUPT STRUCTURE S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 6 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3F8-series microcontrollers. There are 78 instructions.
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INSTRUCTION SET S3F84A5_UM_REV1.10 Table 6-1.
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S3F84A5_UM_REV1.10 INSTRUCTION SET Table 6-1.
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INSTRUCTION SET S3F84A5_UM_REV1.10 Table 6-1.
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S3F84A5_UM_REV1.10 INSTRUCTION SET Table 6-1.
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INSTRUCTION SET S3F84A5_UM_REV1.10 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions. Two other flag bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.
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S3F84A5_UM_REV1.10 INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations have been performed, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.
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INSTRUCTION SET S3F84A5_UM_REV1.10 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3.
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S3F84A5_UM_REV1.10 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working register Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ...
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INSTRUCTION SET S3F84A5_UM_REV1.10 Table 6-5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM BXOR r0–Rb E 3 JP IRR1 SRP/0/1 IM SBC r1,r2 SBC r1,Ir2 SBC R2,R1 SBC IR2,R1 SBC R1,IM BTJR r2.
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S3F84A5_UM_REV1.10 INSTRUCTION SET Table 6-5.
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INSTRUCTION SET S3F84A5_UM_REV1.10 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
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S3F84A5_UM_REV1.10 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3F8-series instruction set. Information is arranged in a consistent format for improved readability and for quick reference.
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INSTRUCTION SET S3F84A5_UM_REV1.10 ADC — Add with Carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple-precision arithmetic, this instruction lets the carry value from the addition of low-order operands be carried into the addition of high-order operands.
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S3F84A5_UM_REV1.10 INSTRUCTION SET ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Unaffected. Z: Set if the two bits are the same; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bit in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination. Flags: No flags are affected. Format: opc dst | b | 0 Bytes Cycles Opcode (Hex) Addr Mode dst 2 4 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address “0” is three bits, and the LSB address value is one bit in length.
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S3F84A5_UM_REV1.10 INSTRUCTION SET BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination. Flags: No flags are affected. Format: opc Bytes Cycles Opcode (Hex) Addr Mode dst 2 4 77 rb dst | b | 1 NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address “b” is three bits, and the LSB address value is one bit in length.
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INSTRUCTION SET S3F84A5_UM_REV1.10 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter. Otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC. Otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or the source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 CALL — Call Procedure CALL dst Operation: SP ← SP–1 @SP ← PCL SP ← SP–1 @SP ← PCH PC ← dst The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
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S3F84A5_UM_REV1.10 INSTRUCTION SET CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 CP — Compare CP dst,src Operation: dst–src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst–src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed.
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INSTRUCTION SET S3F84A5_UM_REV1.10 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst–src ≠ "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise the instruction following the CPIJNE instruction is executed.
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S3F84A5_UM_REV1.10 INSTRUCTION SET DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation.
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INSTRUCTION SET S3F84A5_UM_REV1.10 DA — Decimal Adjust DA (Continued) Example: Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27 (BCD), and the address 27H contains 46 (BCD): ADD DA R1,R0 R1 C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1 ← 3CH + 06 ; ; If an addition is performed using the BCD values 15 and 27, the result should be 42.
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S3F84A5_UM_REV1.10 INSTRUCTION SET DEC — Decrement DEC dst Operation: dst ← dst–1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is ≥ 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect.
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S3F84A5_UM_REV1.10 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
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INSTRUCTION SET S3F84A5_UM_REV1.10 EI — Enable Interrupts EI Operation: SYM (0) ← 1 The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when the EI instruction is executed. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: (See description) The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 6F Addr Mode dst src – – The instruction IDLE stops the CPU clock but it does not stop the system clock.
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INSTRUCTION SET S3F84A5_UM_REV1.10 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 IRET — Interrupt Return IRET IRET (Normal) RET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0").
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S3F84A5_UM_REV1.10 INSTRUCTION SET JP — Jump JP cc,dst (Conditional) JP dst Operation: If cc is true, PC ← dst (Unconditional) The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair.
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INSTRUCTION SET S3F84A5_UM_REV1.10 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the JR instruction is executed. (See the list of condition codes at the beginning of this chapter).
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S3F84A5_UM_REV1.10 INSTRUCTION SET LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 INSTRUCTION SET LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 LDC/LDE — Load Memory LDC dst,src LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr" values an even number for program memory and an odd number for data memory. No flags are affected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1.
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S3F84A5_UM_REV1.10 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
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INSTRUCTION SET S3F84A5_UM_REV1.10 LDCD/LDED — Load Memory and Decrement LDCD dst,src LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI dst,src LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD dst,src LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI dst,src LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Set if the result is > 255; cleared otherwise. Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 NEXT — Next NEXT Operation: PC ← @IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. No flags are affected. Flags: Format: Bytes Cycles Opcode (Hex) 1 10 0F opc Example: The following diagram shows an example of how to use the NEXT instruction.
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S3F84A5_UM_REV1.10 INSTRUCTION SET NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to affect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 FF When the instruction NOP is executed in a program, no operation occurs.
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INSTRUCTION SET S3F84A5_UM_REV1.10 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0" is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET POP — Pop from Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 PUSH — Push to Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: No flags are affected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 CF Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
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INSTRUCTION SET S3F84A5_UM_REV1.10 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement to be executed is the one that is addressed by the new program counter value. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag, as shown in the figure below. 7 0 C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 RLC — Rotate Left through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), and the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 RRC — Rotate Right through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
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S3F84A5_UM_REV1.10 INSTRUCTION SET SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 4F The statement SB0 clears FLAGS.0 to "0", selecting the bank 0 register addressing.
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INSTRUCTION SET S3F84A5_UM_REV1.10 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file. NOTE: Bank 1 is not implemented in some KS88-series microcontrollers. Flags: No flags are affected. Format: opc Example: 6-76 Bytes Cycles Opcode (Hex) 1 4 5F The statement SB1 sets FLAGS.
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S3F84A5_UM_REV1.10 INSTRUCTION SET SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand.
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INSTRUCTION SET S3F84A5_UM_REV1.10 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: opc Example: 6-78 The statement SCF sets the carry flag to “1”.
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S3F84A5_UM_REV1.10 INSTRUCTION SET SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6. 7 6 0 C Flags: C: Set if the bit shifted from the LSB position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.10 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← RP1 (4–7) ← RP1 (3) ← 0 src (4–7), 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1.
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S3F84A5_UM_REV1.10 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
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INSTRUCTION SET S3F84A5_UM_REV1.10 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Set if a "borrow" occurred; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
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S3F84A5_UM_REV1.10 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and the upper four bits of the destination operand are swapped. 7 Flags: 4 3 0 C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 TCM — Test Complement under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result.
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S3F84A5_UM_REV1.10 INSTRUCTION SET TM — Test under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and the source operands are unaffected. Flags: C: Unaffected.
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INSTRUCTION SET S3F84A5_UM_REV1.10 WFI — Wate for Interrupt WFI Operation: The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt. Flags: No flags are affected.
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S3F84A5_UM_REV1.10 INSTRUCTION SET XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different. Otherwise, a "0" bit is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise.
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INSTRUCTION SET S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 7 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW By smart option (3FH.2 – .1 in ROM), user can select internal RC oscillator, or external oscillator. An internal RC oscillator source provides a typical 8 MHz or 0.5 MHz (in VDD = 5 V) depending on smart option. An external crystal or ceramic oscillation source provides a maximum 10 MHz clock. The XIN and XOUT pins connect the oscillation source to the on-chip clock circuit. Simplified crystal/ceramic oscillator circuits are shown in Figures 7-1.
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CLOCK CIRCUIT S3F84A5_UM_REV1.10 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: — In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and current system register values are retained. Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3F84A5, INT0–INT4).
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S3F84A5_UM_REV1.10 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3) After a reset, the fOSC /16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2 or fOSC /8.
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CLOCK CIRCUIT S3F84A5_UM_REV1.10 STOP Control Register (STPCON) D1H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 STOP Control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction Figure 7-4.
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S3F84A5_UM_REV1.10 8 RESET and POWER-DOWN RESET and POWER-DOWN SYSTEM RESET OVERVIEW By smart option (3FH.6 and 3FH.0 in ROM), user can select internal RESET (LVR) or external RESET. The S3F84A5 can be RESET in four ways: — by external power-on-reset — by the external nRESET input pin pulled low — by the digital watchdog peripheral timing out — by Low Voltage Reset (LVR) During an external power-on reset, the voltage at VDD is High level and the nRESET pin is forced to Low level.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 Watchdog RESET External RESETB N.F nRESET Longger than 1us VDD VIN VREF Comparator + When the VDD level is lower than VLVR N.F - Longger than 1us VDD Smart Option 3FH.6 VREF CMOS REF NOTES: 1. The target of voltage detection level is the one you selected at smart option 3FH. 2. CMOS REF is CMOS voltage Reference Figure 8-1.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 MCU Initialization Sequence The following sequence of events occurs during a Reset operation: — All interrupts are disabled. — The watchdog function (basic timer) is enabled. — Ports 0–3 are set to input mode — Peripheral control and data registers reset to their initial values (see Table 8-1). — The program counter is loaded with the ROM reset address, 0100H or other values set by smart option..
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 20μA except that the LVR (Low Voltage Reset) is enabled. All system functions are halted when the clock "freezes", but data stored in the internal register file is retained.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 Sources to Release Stop Mode Stop mode is released when following sources go active: — System Reset by nRESET signal (generated by External nRESET pin or LVR or watchdog reset ) — External Interrupt (INT0-INT4) Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to High level. All system and peripheral control registers are then reset to their default values and the contents of all data registers are retained.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 HARDWARE RESET VALUES The reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. — An "x" means that the bit value is undefined after a reset. — A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 Table 8-2.
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RESET and POWER-DOWN S3F84A5_UM_REV1.10 Table 8-3.
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S3F84A5_UM_REV1.10 9 I/O PORTS I/O PORTS OVERVIEW The S3F84A5 microcontroller has four bit-programmable I/O ports, P0-P3. The port 0 and 3 are 3-bit /5-bit ports and the others are 8-bit ports. This gives a total of 24 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3F84A5 I/O port functions. Table 9-1.
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I/O PORTS S3F84A5_UM_REV1.10 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all four S3F84A5 I/O port data registers. Data registers for ports 0, 1, 2, and 3 have the general format shown in Table 9-2. Table 9-2.
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S3F84A5_UM_REV1.10 I/O PORTS PORT 0 Port 0 is an 3-bit I/O port that you can use two ways: — General-purpose digital I/O — Alternative function Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in Set 1, Bank 0. Port 0 Control Register (P0CON) Port 0 pins are configured individually by bit-pair settings in the control register located: P0CON. When you select output mode, a push-pull or an open-drain circuit is configured.
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I/O PORTS S3F84A5_UM_REV1.10 Port 0 Control Register (P0CON) E6H, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 .5 Not used .4 .3 P0.2 .2 .1 P0.1 /TxD .0 LSB P0.0 /RxD .7 .6 bit XX Not used for S3F84A5 .5 .4 bit/P0.2 00 01 10 11 Input mode Input mode with pull-up Push-pull output Open-drain Output .3 .2 bit/P0.1/TxD 00 01 10 11 Input mode Input mode with pull-up Push-pull output Alternative function: TxD .1 .0 bit/P0.
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S3F84A5_UM_REV1.10 I/O PORTS PORT 1 Port 1 is a 8-bit I/O port with individually configurable pins that you can use two ways: — General-purpose digital I/O — Alternative function Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H in Set 1, Bank 0. Port 1 Control Registers (P1CONH, P1CONL) Port 1 pins are configured individually by bit-pair settings in two control registers located: P1CONL(low byte, E9H, Set 1, Bank 0) and P1CONH(high byte, E8H, Set 1, Bank 0).
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I/O PORTS S3F84A5_UM_REV1.10 Port 1 Control Register, High Byte (P1CONH) E8H, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 .5 P1.7 /ADC7 .4 P1.6 /ADC6 .3 .2 P1.5 /ADC5 .1 .0 LSB P1.4 /ADC4 .7 .6 bit/P1.7/ADC7 00 01 10 11 Input mode Input mode with pull-up Push-pull output Alternative function: ADC7 input .5 .4 bit/P1.6/ADC6 00 01 10 11 Input mode Input mode with pull-up Push-pull output Alternative function: ADC6 input .3 .2 bit/P1.
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S3F84A5_UM_REV1.10 I/O PORTS Port 1 Control Register, Low Byte (P1CONL) E9H, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 .5 P1.3 /ADC3 .4 P1.2 /ADC2 .3 .2 P1.1 /ADC1 /INT1 .1 .0 LSB P1.0 /ADC0 /INT0 .7 .6 bit/P1.3/ADC3 00 01 10 11 Input mode Input mode with pull-up Push-pull output Alternative function: ADC3 input .5 .4 bit/P1.2/ADC2 00 01 10 11 Input mode Input mode with pull-up Push-pull output Alternative function: ADC2 input .3 .2 bit/P1.
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I/O PORTS S3F84A5_UM_REV1.10 Port 1 Interrupt Control Register (P1INT) E7H, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 Not used .5 .4 .3 INT1 .2 INT0 .1 .0 LSB INT1 INT0 .7 .6 bits Not used for S3F84A5 .5 .4 bits INT1 Interrupt Enable/Disable Selection 0x 10 11 Interrupt disable Interrupt enable; falling edge Interrupt enable; rising edge .3 .2 bits INT0 Interrupt Enable/Disable Selection 0x 10 11 Interrupt disable Interrupt enable; falling edge Interrupt enable; rising edge .
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S3F84A5_UM_REV1.10 I/O PORTS PORT 2 Port 2 is an 8-bit I/O port that you can use two ways: — General-purpose I/O — Alternative function Port 2 is accessed directly by writing or reading the port 2 data register, P2 at location E2H, Set 1, Bank 0. Port 2 Control Register (P2CONH, P2CONL) Port 2 pins are configured individually by bit-pair settings in two control registers located: P2CONL (low byte, EBH, Set 1, Bank 0) and P2CONH (high byte, EAH, Set 1, Bank 0).
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I/O PORTS S3F84A5_UM_REV1.10 Port 2 Control Register, High Byte (P2CONH) EAH, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 P2.7 /T0OUT /PWM3A .5 .4 P2.6 /T0CAP /PWM3B .3 .2 .1 P2.5 /TBOUT .0 LSB P2.4 /T0CK/PWM2A .7 .6 bit/P2.7/T0OUT/PWM3A 00 01 10 11 Input mode Input mode with pull-up Push-pull output or PWM3A output Alternative function: T0OUT signal output .5 .4 bit/P2.
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S3F84A5_UM_REV1.10 I/O PORTS Port 2 Control Register, Low Byte (P2CONL) EBH, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 P2.3 /PWM2B .5 .4 P2.2 /TACAP .3 .2 .1 .0 LSB P2.0 /TAOUT/PWM1B P2.1 /TACK/PWM1A .7 .6 bit/P2.3/PWM2B 00 01 10 11 Input mode Input mode with pull-up Push-pull output or PWM2B output Open-drain output .5 .4 bit/P2.2/TACAP 00 01 10 11 Input mode; TACAP input Input mode with pull-up; TACAP input Push-pull output Open-drain output .3 .2 bit/P2.
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I/O PORTS S3F84A5_UM_REV1.10 PORT 3 Port 3 is a 5-bit I/O Port that you can use two ways: — General-purpose I/O — Alternative function Port 3 is accessed directly by writing or reading the port 3 data register, P3 at location E3H, Set 1, Bank 0. Port 3 Control Register (P3CON) Port 3 pins are configured individually by bit-pair settings in two control registers located: P3CONL (EDH, Set 1, Bank 0) and P3CONH (ECH, Set 1, Bank 0).
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S3F84A5_UM_REV1.10 I/O PORTS Port 3 Pull-up Resistor Control Registers (P3PUR) Using the port 3 pull-up control register, P3PUR(F0H, Set 1, Bank 0), you can configure pull-up resistor to individual port 3 pins. Port 3 Control Register, High Byte (P3CONH) ECH, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 .5 .4 .3 Not Used .2 .1 .0 LSB P3.4 .7 .6 bit xx Not used for S3F84A5 .5 .4 bit xx Not used for S3F84A5 .3 .2 bit xx Not used for S3F84A5 .1 .0 bit/P3.
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I/O PORTS S3F84A5_UM_REV1.10 Port 3 Control Register, Low Byte (P3CONL) EDH, Set1, Bank0, R/W, Reset value:00H MSB .7 .6 P3.3 .5 .4 P3.2/INT4 .3 .2 P3.1/INT3 .1 .0 LSB P3.0/INT2 .7 .6 bit/P3.3 00 01 10 11 Input mode Input mode with pull-up Push-pull output Open-drain output .5 .4 bit/P3.2/INT4 00 01 10 11 Input mode/INT4 falling edge interrupt Input mode/INT4 rising edge interrupt Push-pull output Open-drain output .3 .2 bit/P3.
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S3F84A5_UM_REV1.10 I/O PORTS Port 3 Interrupt Control Register (P3INT) EEH, Set1, Bank0, R/W, Reset value: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P3.0/ P3.1/ INT2 P3.2/ INT3 INT4 P3.n bit Failing & Rising Interrupt Enable Selection Bit: 0 1 Disable interrupt Enable interrupt NOTE: "n" is 0, 1 and 2. Figure 9-9. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Register (P3PND) EFH, Set1, Bank0, R/W, Reset value: 00H MSB .7 .6 .5 .4 .3 Not used .2 .1 .
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I/O PORTS S3F84A5_UM_REV1.10 Port 3 Pull-up Resistor Control Register (P3PUR) F0H, Set1, Bank0, R/W, Reset value: 00H MSB .7 .6 .5 .4 .3 Not used .2 .1 .0 LSB P3.0/ P3.1/ INT2 P3.2/ INT3 INT4 P3.n bit Pull-up Resitor Enable/Disable Bit: 0 1 NOTE: Pull-up resistor Disable Pull-up resistor Enable "n" is 0, 1 and 2. Figure 9-11.
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S3F84A5_UM_REV1.10 I/O PORTS PROGRAMMING TIP — Using Ports ORG 0000H ;--------------<< Smart Option >> ORG DB DB DB DB 003CH 0FFH 0FFH 0FFH 98H ; ; ; ; 003CH, must be initialized to 0FFH 003DH, must be initialized to 0FFH 003EH, must be initialized to 0FFH 003FH, nRESET disable, LVR enable (3.9V), internal osc.
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I/O PORTS S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 10 BASIC TIMER BASIC TIMER OVERVIEW Basic Timer (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
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BASIC TIMER S3F84A5_UM_REV1.10 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fOSC/4096.
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S3F84A5_UM_REV1.10 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the oscillator clock divided by 4096 as the BT clock. A reset whenever a basic timer counter overflow occurs.
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BASIC TIMER S3F84A5_UM_REV1.10 Oscillation Stabilization Time Normal Operating mode 0.8 VDD VDD Reset Release Voltage nRESET trst ~ RC Internal Reset Release 0.8 VDD Oscillator (XOUT) Oscillator Stabilization Time BTCNT clock BTCNT value 10000B 00000B tWAIT = (4096x16)/fOSC Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096 x 16/fOSC.
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S3F84A5_UM_REV1.10 BASIC TIMER STOP Mode Normal Operating Mode Normal Operating Mode Oscillation Stabilization Time VDD STOP Instruction Execution STOP Mode Release Signal External Interrupt RESET STOP Release Signal Oscillator (XOUT) BTCNT clock 10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON. BTCON.3 BTCON.
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BASIC TIMER S3F84A5_UM_REV1.10 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specification. ORG 0000H ;--------------<< Smart Option >> ORG DB DB DB DB 003CH 0FFH 0FFH 0FFH 0FFH ; ; ; ; 003CH, must be initialized to 0FF 003DH, must be initialized to 0FF 003EH, must be initialized to 0FF 003FH, nRESET pin enable, LVR disable, External osc.
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S3F84A5_UM_REV1.10 11 8-BIT TIMER A/B 8-BIT TIMER A/B 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector D0H. TAINT also belongs to interrupt level IRQ0, but is assigned the separate vector address, D2H.
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S3F84A5_UM_REV1.10 8-BIT TIMER A/B TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON — Select the timer A operating mode (interval timer, capture mode and PWM mode) — Select the timer A input clock frequency — Clear the timer A counter, TACNT — Enable the timer A overflow interrupt or timer A match/capture interrupt — Timer A start/stop TACON is located at address E4H, Set1 Bank1, and is read/write addressable using Register addressing mode. A reset clears TACON to ‘00H'.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 Timer Interrupt Pending Register (TINTPND) F1H, Set1, Bank1, Reset: 00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 LSB Timer A macth/capture interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Not used Timer 0 overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending .
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S3F84A5_UM_REV1.10 8-BIT TIMER A/B BLOCK DIAGRAM Figure 11-4.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 8-BIT TIMER B OVERVIEW The 8-bit timer B is an 8-bit general-purpose timer/counter.
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S3F84A5_UM_REV1.10 8-BIT TIMER A/B FUNCTION DESCRIPTION Timer B Interrupts The timer B module can generate two interrupts: the timer B overflow interrupt (TBOVF), and the timer B match interrupt (TBINT). TBOVF is interrupt level IRQ1, vector D4H. TBINT also belongs to interrupt level IRQ1, but is assigned the separate vector address, D6H. Timer B overflow interrupt can be cleared by both software and hardware, and match interrupt pending conditions are cleared by software when it has been serviced.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 Table 11-1. Timer B PWM output "stretch" Values for Extension Data Register (TBDATAEX .1−.0) TBDATAEX Bit (Bit1−Bit0) "Stretched" Cycle Number 00 − 01 2 10 1, 3 11 1, 2, 3 Timer B PWM Data 0H Timer B Clock: 100H 200H 4 MHz 00000000B xxxxxx00B 00000001B Register Values: xxxxxx00B (TBDATA TBDATAEX) 10000000B xxxxxx00B 11111110B xxxxxx00B logic 0 250 ns 32 us 250 ns 32 us 250 ns Figure 11-5.
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S3F84A5_UM_REV1.10 8-BIT TIMER A/B 0H 100H Timer B Clock: 4 MHz 500 ns 00000010B xxxxxx01B TBDATA & TBDATAEX : 00000010B : xxxxxx01 B Basic waveform 1st 2nd 3rd 4th 1st 2nd 3rd 4th Extended waveform 0H 100H 4 MHz 750 ns Figure 11-6.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 TIMER B CONTROL REGISTER (TBCON) The control register for the Timer B, TBCON, is located at register address E5H.
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S3F84A5_UM_REV1.10 8-BIT TIMER A/B Timer B Data Register (TBDATA) E7H, Set1, Bank1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: FFh Figure 11-8. Timer B DATA Register (TBDATA) Timer B Extension Data Register (TBDATAEX) EBH, Set1, Bank1, R/W MSB x x x x x x .1 .0 LSB Reset Value: FFh Figure 11-9.
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8-BIT TIMER A/B S3F84A5_UM_REV1.10 BLOCK DIAGRAM TBCON.2 TBCON.7-.5 fxx/512 8-bit Up-Counter (Read Only) fxx/256 fxx/64 M fxx/8 U TINTPND.3 Clear TBCON.3 TBCON.1 Match TBINT Pending 8-bit Comparator X TINTPND.
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S3F84A5_UM_REV1.10 ) 8-BIT TIMER A/B PROGRAMMING TIP — Using the Timer A ;--------------<< Interrupt Vector Address >> ORG 0000H VECTOR 0D0H, INT_TAOVF VECTOR 0D2H, INT_TAINT ;--------------<< Initialize System and Peripherals >> RESET: ORG DI 0100H LD SPL, #0FFH ; Set stack area LD BTCON,#10100011B ; Watchdog disable OR P2CONL,#00000011B ; Configure P2.0 as Timer A output SB1 LD TADATA, #80H ; 6.
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8-BIT TIMER A/B ) S3F84A5_UM_REV1.10 PROGRAMMING TIP — Programming the Timer B "8+2" Bit PWM Mode ;--------------<< Interrupt Vector Address >> ORG 0000H VECTOR 0D4H, INT_TBOVF VECTOR 0D6H, INT_TBINT ;--------------<< Initialize System and Peripherals >> RESET: ORG DI 0100H LD SPL, #0FFH ; Set stack area LD BTCON,#10100011B ; Watchdog disable P2CONH,#00001100B ; Configure P2.5 as Timer B output TBDATA,#80H TBDATAEX,#1H TBCON,#00011111B ; fOSC/1024, clear counter, 8-bit counter OVF int.
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S3F84A5_UM_REV1.10 12 16-BIT TIMER 0 16-BIT TIMER 0 OVERVIEW The S3F84A5 has one 16-bit timer/counter. The 16-bit timer 0 is a 16-bit general-purpose timer/counter.
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16-BIT TIMER 0 S3F84A5_UM_REV1.10 FUNCTION DESCRIPTION Timer 0 Interrupts The timer 0 module can generate two interrupts, the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture interrupt (T0INT). T0OVF is interrupt level IRQ4, vector E2H. T0INT also belongs to interrupt level IRQ4, but is assigned the separate vector address, E4H. A timer 0 overflow interrupt pending condition can be cleared by both software and hardware when it has been serviced.
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S3F84A5_UM_REV1.10 16-BIT TIMER 0 TIMER 0 CONTROL REGISTER (T0CON) You use the Timer 0 control register, T0CON, to — Select the Timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the Timer 0 input clock frequency — Clear the Timer 0 counter. — Enable the Timer 0 overflow interrupt — Enable the Timer 0 match/capture interrupt T0CON is located at address E8H, Set1 Bank1, and is read/write addressable using Register addressing mode. A reset clears T0CON to ‘00H’.
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16-BIT TIMER 0 S3F84A5_UM_REV1.10 Timer Interrupt Pending Register (TINTPND) F1H, Set1, Bank1, Reset: 00H, R/W MSB .7 .6 Timer 0 overflow interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending Timer 0 match interrupt pending flag: 0 = Not pending (clear pending bit) 1 = Interrupt pending .5 .4 Not used .3 .2 .1 .
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S3F84A5_UM_REV1.10 16-BIT TIMER 0 BLOCK DIAGRAM T0CON.7-.5 T0CON.0 fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 T0CK Overflow Pending Data Bus TINTPND.7 8 M U X 16-bit Up-Counter (Read Only) T0OVF Clear T0CON.2 VSS 16-bit Comparator T0CAP M U X T0CON.1 Match M U X T0INT Pending TINTPND.6 16-bit Timer Buffer T0OUT CTL Overflow T0OVF In PWM mode High level when data > counter Low level when data < counter T0CON.4.3 16-bit Timer Data Register (T0DATAH/L) T0CON.4.3 8 Data Bus NOTES: 1.
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16-BIT TIMER 0 ) S3F84A5_UM_REV1.10 PROGRAMMING TIP — Using the Timer 0 ORG 0000h VECTOR 0E4h, INT_Timer0_match ORG 0100h DI LD LD SPL, #0FFH BTCON, #10100011B LD LD T0DATAH, #00H T0DATAL, #0F0H LD T0CON,#01000110B INITIAL: EI MAIN: • • • MAIN ROUTINE • • • JR T, MAIN INT_Timer0_match: • • • Interrupt service routine • • • IRET .END 12-6 ; Set stack area ; Disable Watch-dog ; fxx/256, interval, clear counter, Enable interrupt ; Duration 7.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 13 8-BIT PWM (PULSE WIDTH MODULATION) OVERVIEW This microcontroller’s PWM module has one 8-bit counter and two PWM waveform generation circuits. It is delicately designed to fit the 3-phase motor control applications. The PWM module has the following features: − Two operation modes: edge and center aligned PWM − Up to six PWM outputs that are internally divided into 2 groups (group A and group B).
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PWM Counter The PWM 8-bit counter is a bi-directional counter. Depending on the PWM mode, the counter can run increasingly or decreasingly. In edge aligned mode, the counter up-counts from 00H to FFH, and then automatically restarts from 00H. In center aligned PWM mode, the counter first up-counts from 00H until it reaches FFH, and then down-counts from FFH to 00H, hence finishes the first cycle and repeatedly starts the next.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PWM Mode The PWM module has two operation modes. Edge aligned PWM mode and center aligned PWM mode which can be selected by writing PWMCON.4. Edge Aligned PWM Mode In edge aligned PWM mode, counter counts from 00H to FFH then restarts from 00H. In non-inverted mode, the corresponding PWM output is cleared on compare match, and set at FFH. In inverted mode, the output is set on compare match and cleared at FFH.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 Center Aligned PWM Mode In center aligned PWM mode, counter counts from 00H to FFH and then from FFH to 00H. In non-inverted mode, the PWM output is cleared on the compare match while up-counting, and set on the compare match while downcounting. In inverted mode, the output is set on the compare match while up-counting and cleared on the compare match while down-counting.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 Programmable Dead-time generation In motor control applications, the power output devices (such as MOSFET) cannot switch instantaneously, some amount of time must be provided between the turn-off event of one transistor and the turn-on event of the other transistor in a complementary pair. In center aligned mode, user can obtain 3 pairs of complementary PWM output with dead-time by the following steps: 1.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 Table 13-1. PWM selectable waveform mode and group compare output mode for PWM Control Register PWM Waveform Mode Bit (PWMCON.4) PWM Output Mode Bit (PWMCON.3/.2) Description of Waveform Generator • Clear PWM output pin on Compare Match. 0 0 • Set PWM output pin at FFH. • Set PWM output pin on Compare Match. 0 1 • Clear PWM output pin at FFH. • Clear PWM output pin on Compare Match when up-counting.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address F1H, Set 1, Bank 0.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PORT2 PWM OUTPUT CONTROL REGISTER (P2PWMOUT) The port 2 PWM output control register for the PWM module, P2PWMOUT, is located at register address F2H, Set 1, Bank 0. Bit settings in the P2PWMOUT register control the following function: — Normal I/O output or PWM output selection A reset clears all P2PWMOUT bits to logic zero, selecting all PWM output I/O pins as normal output pins.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PWM INTERRUPT CONTROL REGISTER (PWMINT) The PWM interrupt control register, PWMINT, is located at register address F4H, Set 1, Bank 0. When the interrupt enable bit of any PWM interrupt is "1", the occurrence of counter overflow or compare match of each group will set the corresponding PWM pending bit and generate an interrupt request.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 PWM COMPARE DATA REGISTER (PWMADATA & PWMBDATA) There are two compare data registers for the 2 PWM groups: Group A compare data register PWMADATA (E4H, Set 1, Bank 0), Group B compare data register PWMBDATA (E5H, Set 1, Bank 0). PWM A Group Compare Data Register (PWMADATA) E4H, Set1, Bank0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Reset Value: 00h PWM B Group Compare Data Register (PWMBDATA) E5H, Set1, Bank0, R/W MSB .7 .6 .5 .4 .3 .2 .
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 BLOCK DIAGRAM PENDING PWMINT.2 PWMINT.7 PWMCON.1 fxx/256 fxx/64 fxx/8 fxx CLR M U X P2.7 I/O output Counter overflow PENDING PWMINT.1 PWMINT.6-.5 Direction PWMCON.7-.6 Logic To P2.7/PWM3A I/O pin P2PWMOUT.7 P2.4 I/O output 8-bit Counter PWMCON.0 M U X PWMA Group match 8-bit Comparator A PWMADATA Buffer PWMCON.4 M U X Waveform Generator Overflow PWMCON.3 PWMCON.4 P2PWMOUT.4 P2.1 I/O output M U X PWMADATA 8 To P2.
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8-BIT PWM (PULSE WIDTH MODULATION) ) S3F84A5_UM_REV1.10 PROGRAMMING TIP — Programming the PWM Module to output 6 channels Edge Aligned PWM ;--------------<< Interrupt Vector Address >> ORG 0000H VECTOR 0DEH, INT_PWMOVF VECTOR 0E0H, INT_PWMAMATCH VECTOR 0F0H, INT_PWMBMATCH ;--------------<< Initialize System and Peripherals >> RESET: ORG DI 0100H LD BTCON,#10100011B ; Watchdog disable AND LD LD P2,#00100100B P2CONH,#10100010B P2CONL,#10001010B ; Configure P2.7,P2.6,P2.4,P2.3,P2.1,P2.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.10 ) PROGRAMMING TIP — Programming the PWM Module to 3 complementary outputs in Center Aligned mode (BLDC Motor Control application) PWM frequency: 15.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.
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8-BIT PWM (PULSE WIDTH MODULATION) S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.
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UART S3F84A5_UM_REV1.10 UART CONTROL REGISTER (UARTCON) The control register for the UART is called UARTCON at address F5H, Set1 Bank0. It has the following control functions: — Operating mode and baud rate selection — Multiprocessor communication and interrupt control — Serial receive enable/disable control — 9th data bit location for transmit and receive operations (mode 2) — UART transmit and receive interrupt control A reset clears the UARTCON value to "00H".
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S3F84A5_UM_REV1.10 UART UART INTERRUPT PENDING REGISTER (UARTPND) The UART interrupt pending register, UARTPND is located at address F6H, Set1 Bank0. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.1). In mode 0 of the UART module, the receive interrupt pending flag UARTPND.1 is set to "1" when the 8th receive data bit has been shifted. In mode 1 or 2, the UARTPND.1 bit is set to "1" at the halfway point of the stop bit's shift time.
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UART S3F84A5_UM_REV1.10 UART DATA REGISTER (UDATA) UART Data Register (UDATA) F8H, Set1, Bank0, R/W, Reset Value: FFH .7 MSB .6 .4 .5 .3 .2 .1 .0 LSB Transmit or Receive data Figure 14-3. UART Data Register (UDATA) UART BAUD RATE DATA REGISTER (BRDATA) The value stored in the UART baud rate register, (BRDATA), lets you determine the UART clock rate (baud rate). UART Baud Rate Data Register (BRDATA) F7H, Set1, Bank0, R/W, Reset Value: FFH MSB .7 .6 .5 .4 .3 .2 .1 .
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S3F84A5_UM_REV1.10 UART BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register, 8bit BRDATA Mode 0 Mode 1 Mode 2 Mode 3 baud rate baud rate baud rate baud rate = fxx/(16 × (8Bit BRDATA + 1)) = fxx/(16 × (8Bit BRDATA + 1)) = fxx/16 = fxx/(16 × (8Bit BRDATA + 1)) Table 14-1. Commonly Used Baud Rates Generated by 8-bit BRDATA Mode Baud Rate Oscillation Clock BRDATA Decimal Hex Mode 2 0.
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UART S3F84A5_UM_REV1.10 BLOCK DIAGRAM SAM8 Internal Data Bus TB8 fxx MS0 MS1 8 BIT BRDATA S D Q CLK Baud Rate Generator Write to UDATA UDATA CLK Zero Detector Tx Control RxD (P0.0) TxD (P0.1) Shift Start Tx Clock MS0 MS1 EN Send TIP TxD (P0.1) TIE Interrupt RIE Rx Clock RE RIE 1-to-0 Transition Detector MS0 MS1 Shift Clock RIP Receive Rx Control Shift Start Shift Value Bit Detector Shift Register UDATA RxD (P0.0) SAM8 Internal Data Bus Figure 14-5.
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S3F84A5_UM_REV1.10 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P0.0) pin and TxD (P0.1) pin outputs the shift clock. Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first. Mode 0 Transmit Procedure 1. Select mode 0 by setting UARTCON.6 and .7 to "00B". 2. Write transmission data to the shift register UDATA (F8H) to start the transmission operation. Mode 0 Receive Procedure 1.
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UART S3F84A5_UM_REV1.10 UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10-bits are transmitted (through the TxD (P0.1) pin) or received (through the RxD (P0.0) pin). Each data frame has three components: — Start bit ("0") — 8 data bits (LSB first) — Stop bit ("1") When receiving, the stop bit is written to the RB8 bit in the UARTCON register. The baud rate for mode 1 is variable. Mode 1 Transmit Procedure 1. Select the baud rate generated by 8bit BRDATA. 2.
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S3F84A5_UM_REV1.10 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2, 11-bit are transmitted through the TxD pin or received through the RxD pin. In mode 2, the baud rate is fixed at fxx/16. Each data frame has three components: — Start bit ("0") — 8 data bits (LSB first) — Programmable 9th data bit — Stop bit ("1") The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UARTCON0.3).
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UART S3F84A5_UM_REV1.10 UART MODE 3 FUNCTION DESCRIPTION In mode 3, 11-bits are transmitted (through the TxD) or received (through the RxD). Mode 3 is identical to mode 2 but can be configured to variable baud rate. Each data frame has four components: — Start bit ("0") — 8 data bits (LSB first) — Programmable 9th data bit — Stop bit ("1") Mode 3 Transmit Procedure 1. Select the baud rate generated by setting BRDATA. 2. Select mode 3 (9-bit UART) by setting UARTCON bits 6 and 7 to '11B'.
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S3F84A5_UM_REV1.10 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3F8-series multiprocessor communication features let a "master" S3F84A5 send a multiple-frame serial message to a "slave" device in a multi- S3F84A5 configuration. It does this without interrupting other slave devices that may be on the same serial line. This feature can be used only in UART mode 2 or 3 with the parity disable mode. In mode 2 and 3, 9 data bits are received. The 9th bit value is written to RB8 (UARTCON.2).
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UART S3F84A5_UM_REV1.10 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications: 1. Set all S3F84A5 devices (masters and slaves) to UART mode 2 or 3 2. Write the MCE bit of all the slave devices to "1". 3. The master device's transmission protocol is: — First byte: the address identifying the target slave device (9th bit = "1") — Next bytes: data (9th bit = "0") 4.
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S3F84A5_UM_REV1.10 15 10-BIT A/D CONVERTER 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the 8 input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and VSS values.
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10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 The A/D converter then enters an idle state. If you are not using event trigger, you should reset ADCONH.0 to start another conversion. Remember to read the contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. A/D conversion complete interrupt pending bit should be cleared by software. ADCON.
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S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER A/D CONVERTER HIGH BYTE CONTROL REGISTER (ADCONH) The A/D converter high-byte control register, ADCONH, is located at address FBH, Set1 Bank0. It has four functions: — Analog input pin selection (bits 4, 5, and 6) — A/D conversion End-of-conversion (EOC) status (bit 3) — A/D conversion clock source selection (bits 1,2) — A/D operation start (bit 0) After a reset, the start bit is turned off. You can select only one analog input channel at a time.
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10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 A/D Converter High-byte Control Register (ADCONH) FBH, Set1, Bank0, Reset=00H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
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S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER Conversion Data Register High Byte (ADDATAH) F9H, Set1, Bank0, Read only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Conversion Data Register Low Byte (ADDATAL) FAH, Set1, Bank0, Read only MSB x x x x x x .1 .0 LSB Figure 15-4. A/D Converter Data Register (ADDATAH/L) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage.
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10-BIT A/D CONVERTER S3F84A5_UM_REV1.10 BLOCK DIAGRAM - A/D Converter High Byte Control Register ADCONH (FBH) ADCONH.6-.4 ADC0/P1.0 ADC1/P1.1 ADC2/P1.2 ADC6/P1.6 ADC7/P1.7 ADC Start M U L T I P L E X E R Control Circuit Clock Selector ADCONH.3 (EOC Flag) ADCONH.2-.1 R CHold + - ADCONL.0 Pending Successive Approximation Circuit ADCONL.1 Analog Comparator A/D Conv. Complete Interrupt AVref D/A Converter VSS Conversion Result ADDATAH (F9H) ADDATAL (FAH) ADCONL.6-.4 ADC conv.
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S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of VSS and AVREF. 2. Configure P1.0–P1.7 for analog input before A/D conversions. To do this, you load the appropriate value to the P1CONH and P1CONL (for ADC0–ADC7) registers. 3. Before the conversion operation starts, you must first select one of the eight input pins (ADC0–ADC7) by writing the appropriate value to the ADCONH register. 4.
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10-BIT A/D CONVERTER S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 10-BIT A/D CONVERTER PROGRAMMING TIP — Configuring A/D Converter (2) End of ADC conversion complete: A/D converter conversion complete interrupt Event trigger : A/D converter conversion complete interrupt (successive conversion) ADC Conversion Speed: 20us(typical) @ fADC = 2.
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10-BIT A/D CONVERTER S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 16 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW By smart option (3FH.6 in ROM), user can select internal RESET (LVR) or external RESET. The S3F84A5 can be reset in four ways: — by external power-on-reset — by the external reset input pin pulled low — by the digital watchdog timing out — by the Low Voltage reset circuit (LVR) During an external power-on reset, the voltage VDD is High level and the RESETB pin is forced Low level.
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LOW VOLTAGE RESET S3F84A5_UM_REV1.10 Watchdog RESET External RESETB N.F nRESET Longger than 1us VDD VIN Comparator + VREF When the VDD level is lower than VLVR N.F - Longger than 1us VDD Smart Option 3FH.6 VREF CMOS REF NOTES: 1. The target of voltage detection level is the one you selected at smart option 3FH. 2. CMOS REF is CMOS voltage Reference Figure 16-1.
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S3F84A5_UM_REV1.10 17 Embedded Flash Memory Interface EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F84A5 has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want. The S3F84A5‘s embedded 16K-byte memory has two operating features as below: — User Program Mode — Tool Program Mode: Refer to the chapter 20.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can store On Board Program Software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISPTM sectors can’t be erased or programmed by ‘LDC’ instruction for the safety of On Board Program Software. The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart Option.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface Figure 17-2.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON register is available only in user program mode to select the flash memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection. Flash Memory Control Register (FMCON) F4H , Set1 , Bank1 , R/W MSB .7 .6 .5 .4 .3 .2 .1 .
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Address Sector Register High Byte) indicates the high byte of sector address. One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode. The only unit of flash memory to be erased in the user program mode is a sector. The program memory of S3F84A5, 16Kbytes flash memory, is divided into 128 sectors. Every sector has all 128byte sizes. So the sector to be located destination address should be erased first to program a new data (one byte) into flash memory.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 2. Set Flash Memory Sector Address Register (FMSECH and FMSECL). 3. Set Flash Memory Control Register (FMCON) to “10100001B”. 4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR: SB1 LD LD LD LD ERASE_STOP: LD SB0 FMUSR,#0A5H FMSECH,#04H FMSECL,#00H FMCON,#10100001B ; User program mode enable ; Set sector address 0400H,sector 8, ; Select erase mode enable & Start sector erase FMUSR,#00H ; User program mode disable Case2.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 SECTOR_ERASE: LD LD MULT MULT ADD R12,SecNumH R14,SecNumL RR12,#80H RR14,#80H R13,R14 ; Calculation the base address of a target sector ; The size of one sector is 128-bytes ; BTJRF FLAGS.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must erase target sectors before programming. 2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 3. Set Flash Memory Control Register (FMCON) to “0101000XB”. 4.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 Start SB1 ; Select Bank1 FMSECH FMSECL High Address of Sector Low Address of Sector R(n) R(n+1) R(data) High Address to Write Low Address to Write 8-bit Data FMUSR FMCON LDC #0A5H #01010000B @RR(n),R(data) FMUSR #00H SB0 ; Set Secotr Base Address ; Set Address and Data ; User Program Mode Enable ; Mode Select ; Write data at flash ; User Program Mode Disable ; Select Bank0 Finish 1-BYTE Writing Figure 17-9.
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S3F84A5_UM_REV1.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 PROGRAMMING TIP — Programming Case1.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface Case3.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.10 READING The read operation starts by ‘LDC’ instruction. The program procedure in user program mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3.
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S3F84A5_UM_REV1.10 Embedded Flash Memory Interface HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution in the tool program mode. In terms of user program mode, the procedure of setting Hard Lock Protection is following that.
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Embedded Flash Memory Interface S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 18 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3F84A5 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Table 18-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Symbol Conditions Rating Unit VDD − − 0.3 to + 6.5 V Input voltage VI All input ports − 0.3 to VDD + 0.3 V Output voltage VO All output ports − 0.3 to VDD + 0.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Table 18-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Operating Symbol VDD Voltage Conditions fx = 0.4−4MHz , LVR off fx = 0.4−4MHz , LVR on fx = 0.4−10MHz Input high voltage VIH1 VDD= 2.0 to 5.5 V Min Typ Max Unit − 5.5 V VLVR − 5.5 4.5 − 5.5 0.8 VDD − VDD V − 0.2 VDD V 2.0 (Note) All Ports except VIH2 and VIH3 VIH2 nRESET 0.85 VDD VIH3 VDD= 2.0 to 5.5 V VDD − 0.3 XIN and XOUT VDD= 2.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Table 18-2. D.C. Electrical Characteristics (Continued) (TA = − 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Supply current Symbol Conditions Min Typ Max Unit mA IDD1 RUN mode 10MHz CPU clock VDD = 2.0 to 5.5 V − 6 12 IDD2 Idle mode 10MHz CPU clock VDD = 2.0 to 5.5 V − 3 5 IDD3 Stop mode, LVR disable VDD = 2.0 to 5.5 V − 2.5 6 − − 15 − 35 70 TA = 25 °C VDD = 2.0 to 5.5 V TA = 85 °C Stop mode, LVR enable VDD = 2.0 to 5.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Table 18-3. A.C. Electrical Characteristics (TA = –40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width tINTH, tINTL Port 1(INT0, INT1) Port 3(INT2−INT4) VDD = 5V ± 10% 500 − − ns nRESET input low width tRSL Input VDD = 5V ± 10% 10 − − us 1/tCPU tINTL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tcpu means one CPU clock period. Figure 18-1. Input Timing for External Interrupts tRSL RESET 0.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 CPU Clock 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz 0.4 MHz 1 2 3 4 4.5 5 5.5 6 7 Supply Voltage (V) Figure 18-3.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Table 18-4. Oscillator Characteristics (TA = – 40 °C to + 85 °C) Oscillator Main crystal or ceramic Clock Circuit XIN XOUT C1 External clock (Main system) High/Low speedInternal RC oscillator Test Condition Min Typ Max Unit VDD = 4.5 to 5.5 V 0.4 − 10 MHz VDD = 4.5 to 5.5 V 0.4 − 10 MHz High Speed VDD = 5 V, TA =25°C − 8 − MHz Low Speed VDD = 5 V, TA =25°C − 0.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Table 18-5. Oscillation Stabilization Time (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit ms Main crystal fosc > 1.0 MHz − − 20 Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Table 18-6. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5V) Parameter Symbol Conditions Data retention supply voltage VDDDR Stop mode Data retention supply current IDDDR Stop mode; VDDDR = 2.0 V Min Typ Max Unit 1.2 − 5.5 V − − 5 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Oscillation Stabilization Time ~ ~ Idle Mode Stop Mode Data Retention Mode ~ ~ V DD V DDDR Normal Operating Mode Execution of STOP Instruction Interrupt 0.2 V DD NOTE: tWAIT tWAIT is the same as 4096 x 16 x 1/fosc Figure 18-5. Stop Mode Release Timing Initiated by Interrupts Table 18-7. LVR (Low Voltage Reset) Circuit Characteristics (TA = 25 °C) Parameter Low voltage reset 18-10 Symbol Conditions Min Typ Max Unit VLVR − 2.0 2.7 3.5 2.3 3.0 3.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Table 18-8. UART Timing Characteristics in Mode 0 (10 MHz) (TA = – 40°C to + 85°C, 2.0 V to 5.5 V, Load capacitance = 80 pF) Parameter Symbol Min Typ.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Table 18-9. A/D Converter Electrical Characteristics (TA = − 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions VDD = 5.12 V Total accuracy Min Typ Max Unit − − ±3 LSB LSB ADC clock = 2.5 MHz AVREF = 5.
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S3F84A5_UM_REV1.10 ELECTRICAL DATA Digital Output Analog Input AVSS VEOB V2 V(K-1) V(K) VEOT AVREF Figure 18-7. Definition of DLE and ILE Table 18-10. AC Electrical Characteristics for Internal Flash ROM (TA = –25 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Flash Erase/Write/Read Voltage Fewrv VDD 2 5 5.5 V Ftp 20 30 40 μS Ftp1 10 15 20 mS Chip Erasing Time (3) Ftp2 30 50 70 mS Data Access Time FtRS VDD = 2.
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ELECTRICAL DATA S3F84A5_UM_REV1.10 Figure 18-8. The Circuit Diagram to Improve EFT Characteristics NOTE: To improve EFT characteristics, we recommend using power capacitor near S3F84A5 like Figure 18-9. Table 18-11.
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S3F84A5_UM_REV1.10 19 MECHANICAL DATA MECHANICAL DATA OVERVIEW 8 The S3F84A5 is available in a 28-pin SOP package (28-SOP-375) , 28-pin SSOP package (28-SSOP- ) and a 32-pin ELP package (32-ELP-0505). Package dimensions are shown in Figures 19-1, 19-2 and 19-3. #1 #14 17.62 ? 0.2 (0.56) 0.41 ? 0.1 1.27 + 0.10 - 0.05 0.05 MIN 2.15 ? 0.1 18.02 MAX 0.15 0.60 ? 0.2 28-SOP-375 9.53 7.70 ? 0.2 #15 2.50 MAX 10.45 ? 0.3 #28 NOTE: Dimensions are in millimeters Figure 19-1.
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S3F84A5_UM_REV1.10 8 MECHANICAL DATA #1 #14 10.20 ? 0.14 (?) 0.32 ? 0.08 0.65 0.05 MIN 1.73 ± 0.1 10.34 MAX 0.18 NOTE: Dimensions are in millimeters Figure 19-2. 28-SSOP- ? Package Dimensions 19-2 + 0.07 - 0.08 0.75 ± 0.19 28-SSOP-? 7.10 5.25 ± 0.13 #15 1.98 MAX 6.9? ± 0.
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S3F84A5_UM_REV1.10 MECHANICAL DATA Figure 19-3.
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MECHANICAL DATA S3F84A5_UM_REV1.
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S3F84A5_UM_REV1.10 20 S3F84A5 FLASH MCU S3F84A5 FLASH MCU OVERVIEW The S3F84A5 single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. VSS XOUT/P3.3 XIN/P3.4 (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S3F84A5 (Top View) 28-SOP 28-SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P3.2/INT4 (SCLK) P3.
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PWM2A/T0CK/P2.4 26 TBOUT/P2.5 27 P1.7/ADC7 P1.6/ADC6 P1.5/ADC5 20 19 18 P1.4/ADC4 P2.0/TAOUT/PWM1B 21 17 P2.1/TACK/PWM1A 22 25 P2.2/TACAP 24 PWM2B/P2.3 23 S3F84A5_UM_REV1.10 NC S3F84A5 FLASH MCU 16 NC 15 P1.3/ADC3 14 P1.2/ADC2 13 P1.1/ADC1/INT1 NC 32 9 RxD/P0.0 P0.2/nRESET 8 10 7 31 (Vpp)TEST NC 6 AVREF Xin/P3.4 11 5 32-ELP Xout/P3.3 30 4 INT2/P3.0 VSS P1.0/ADC0/INT0 3 12 VDD (Top View) 2 29 (SCLK)INT4/P3.2 PWM3A/T0OUT/P2.7 1 28 (SDAT)INT3/P3.
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S3F84A5_UM_REV1.10 S3F84A5 FLASH MCU Table 20-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name P3.1 During Programming Pin Name SDAT Pin No. 26 (28-pin) I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as an Input or push-pull output port. I/O Serial clock pin. Input only pin. 1 (32-pin) P3.
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S3F84A5 FLASH MCU S3F84A5_UM_REV1.10 ON BOARD WRITING The S3F84A5 needs only 6 signal lines including VDD and GND pins for writing internal flash memory with serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of application board is designed. Circuit design guide At the flash writing, the writing tool needs 6 signal lines that are GND, VDD, RESET, TESET, SDA and SCL.
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S3F84A5_UM_REV1.10 S3F84A5 FLASH MCU Reference Table for Connection Pin Name I/O mode in Applications Resistor (need) Vpp(TEST) Input Yes Required value RVpp is 10 Kohm ~ 50 Kohm. CVpp is 0.01uF ~ 0.02uF. RESET SDA(I/O) SCL(I/O) Input Yes Input Yes Output No(Note) Input Yes Output No(Note) RRESET is 2 Kohm ~ 5 Kohm. CRESET is 0.01uF ~ 0.02uF. RSDA is 2 Kohm ~ 5 Kohm. RSCL is 2 Kohm ~ 5 Kohm. - NOTE1: In on-board writing mode, very high-speed signal will be provided to pin SCL and SDA.
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S3F84A5_UM_REV1.10 21 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 Bus [Development System Configuration] Figure 21-1.
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS TB84A5 TARGET BOARD The TB84A5 target board is used for development of S3F84A5 microcontrollers. The TB84A5 target board is operated as target CPU with Emulator (SK-1200, OPENice-i500/2000). Figure 21-2. TB84A5 Target Board Configuration NOTE: TB84A5 should be supplied 5V normally. So the power supply from Emulator should be set 5V for the target board operation.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 Table 21-1. Components of TB84A5 Symbols Usage Description J1 100-pin connector Connection between emulator and TB84A5 target board.
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 21-3.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 Table 21-4. Using Single Header Pins to Select Clock Source and Operation mode Target Board Part JP6 X-TAL Clock Source JP6 Comments Use external crystal or ceramic oscillator as the system clock. X-TAL Clock Source Use SMDS2/SMDS2+ internal clock source as the system clock. TEST MODE RUN Mode RUN MODE JP1 TEST MODE TEST Mode RUN MODE JP1 Main MODE The S3E84A0 runs in main mode, just the same as S3F84A5. The debug interface is not available.
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 3F.6 3F.5 3F.4 3F.3 3F.2 3F.1 3F.0 3E.7 3E.6 3E.5 3E.4 3E.3 3E.2 3E.1 3E.0 OFF OFF SW3 SW2 ON ON ON Low OFF High ( Default) NOTES: 1. For EVA chip, smart option is determined by DIP switch not software. 2. Please keep the reserved bits (3FH.3, 3EH.4-.3) as default value (high). Figure 21-3. DIP Switch for Smart Option NOTE: P0.2/nRESET pin can be used as normal I/O only when both 3FH.6 & 3FH.0 are set ON. Table 21-5.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 Table 21-6. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Triggers Connector from External Trigger Sources of the Application System Ch1 Ch2 You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. IDLE LED This LED is ON when the evaluation chip (S3E84A0) is in idle mode.
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS J2 1 1 1 32 33 44 5 6 6 7 8 99 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 18 19 20 S3C84T5 40-PIN DIP SOCKET VSS X OUT/P3.3 X IN/P3.4 (Vpp)TEST RxD/P0.0 TxD/P0.1 nRESET/P0.2 AVREF INT0/ADC0/P1.0 INT1/ADC1/P1.1 ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5 NC1 NC2 NC3 NC4 NC5 NC6 (Top View) 32-SDIP 40 32 39 4 38 30 37 29 36 28 27 35 26 34 25 33 32 31 23 30 22 29 21 28 20 19 27 18 26 25 24 23 22 21 VDD P3.2/INT4(SCLK) P3.1/INT3(SDAT) P3.0/INT2 P2.7/T0OUT/PWM3A P2.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 THIRD PARTIES FOR DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG Incircuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS 8-BIT IN-CIRCUIT EMULATOR OPENice - i500 AIJI System • TEL: 82-31-223-6611 • FAX: 82-331-223-6613 • E-mail: openice@aijisystem.com stroh@yicsystem.com • URL: http://www.aijisystem.com OPENice - i2000 AIJI System • TEL: 82-31-223-6611 • FAX: 82-331-223-6613 • E-mail: openice@aijisystem.com stroh@yicsystem.com • URL: http://www.aijisystem.com SK-1200 Seminix • • • • TEL: 82-2-539-7891 FAX: 82-2-539-7819 E-mail: sales@seminix.com URL: http://www.seminix.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.10 OTP/MTP PROGRAMMER (WRITER) SPW-uni SEMINIX Single OTP/ MTP/FLASH Programmer • TEL: 82-2-539-7891 • FAX: 82-2-539-7819. • E-mail: sales@seminix.com • URL: http://www.seminix.com • Download/Upload and data edit function • PC-based operation with USB port • Full function regarding OTP/MTP/FLASH MCU programmer (Read, Program, Verify, Blank, Protection..
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S3F84A5_UM_REV1.10 DEVELOPMENT TOOLS OTP/MTP PROGRAMMER (WRITER) (Continued) GW-uni SEMINIX Gang Programmer for OTP/MTP/FLASH MCU • 8 devices programming at one time • Fast programming speed :OTP(2Kbps) / MTP (10Kbps) • Maximum buffer memory:100Mbyte • Operation mode: PC base / Stand-alone(no PC) • Support full functions of OTP/MTP (Read, Program, Checksum, Verify, Erase, Read protection, Smart option) • Simple GUI(Graphical User Interface) • Device information setting by a device part no.
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DEVELOPMENT TOOLS S3F84A5_UM_REV1.