User`s manual

CONTROL REGISTERS S3F84A5_UM_REV1.10
4-40
TINTPND — Timer Interrupt Pending Register F1H Set 1, Bank 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
0 0 – – 0 0 0 0
Read/Write
R/W R/W – – R/W R/W R/W R/W
.7 Timer 0 Overflow Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending
.6 Timer 0 Match/Capture Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending
.5-.4 Not used for S3F84A5
.3 Timer B Overflow (only for 8-bit counter overflow) Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending
.2 Timer B Match (only for 8-bit reference data match) Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending
.1 Timer A Overflow Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending
.0 Timer A Match/Capture Interrupt Pending Bit
0 No interrupt pending (Clear pending bit when write)
1 Interrupt pending