User`s manual

I/O PORTS S3F84A5_UM_REV1.10
9-8
Port 1 Interrupt Control Register (P1INT)
E7H, Set1, Bank0, R/W, Reset value:00H
LSBMSB .7 .6 .5 .4 .3 .2 .1 .0
Not used
.7 .6 bits Not used for S3F84A5
INT1
INT0
.1 bits INT1 Pending bit
.0 bits INT0 Pending bit
.5 .4 bits INT1 Interrupt Enable/Disable Selection
0x
10
11
Interrupt disable
Interrupt enable; falling edge
Interrupt enable; rising edge
.3 .2 bits INT0 Interrupt Enable/Disable Selection
0x
10
11
Interrupt disable
Interrupt enable; falling edge
Interrupt enable; rising edge
INT1
INT0
No interrupt pending (when read)
Pending bit clear (when write)
Interrupt is pending (when read)
No effect (when write)
0
0
1
1
No interrupt pending (when read)
Pending bit clear (when write)
Interrupt is pending (when read)
No effect (when write)
0
0
1
1
Figure 9-4. Port 1 Interrupt Control Register (P1INT)