User`s manual

8-BIT TIMER A/B S3F84A5_UM_REV1.10
11-2
FUNCTION DESCRIPTION
Timer A Interrupts
The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/
capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector D0H. TAINT also belongs to interrupt level IRQ0,
but is assigned the separate vector address, D2H.
Timer A overflow interrupt can be cleared by both software and hardware, and match/capture interrupt pending
conditions are cleared by software when it has been serviced.
Interval Timer Mode
The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt
level IRQ0, and is assigned the separate vector address, D2H.
When timer A match interrupt occurs and is serviced by the CPU, the pending condition is cleared by software.
In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to
the value written to the Timer A reference data register, TADATA. The match signal generates a timer A match
interrupt(TAINT , vector D2H) and clears the counter.
If, for example, you write the value 10H to TADATA and 0BH to TACON, the counter will increment until it reaches
10H. At this point the TA interrupt request is generated, the counter value is reset, and counting resumes.
Capture Mode
In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter
value into the Timer A data register. You can select rising or falling edges to trigger this operation.
Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by
setting the value of the timer A capture input selection bit in the Port 2 low–byte control register, P2CONL, (EBH,
Set1 Bank0).
When P2CONL.5.4 is 00 and 01, the TACAP input or normal input is selected. When P2CONL.5.4 is set to 10 and
11, output is selected.
Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated
whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value
is loaded into the Timer A data register.
By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
TAOUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value
written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead,
it runs continuously, overflowing at FFH, and then continues incrementing from 00H.
Although you can use the match or the overflow interrupt in PWM mode, these interrupts are not typically used in
PWM-type applications. Instead, the pulse at the TAOUT pin is held to Low level as long as the reference data
value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data
value is greater than ( > ) the counter value. One pulse width is equal to t
CLK
• 256 .