User`s manual

16-BIT TIMER 0 S3F84A5_UM_REV1.10
12-2
FUNCTION DESCRIPTION
Timer 0 Interrupts
The timer 0 module can generate two interrupts, the timer 0 overflow interrupt (T0OVF), and the timer 0
match/capture interrupt (T0INT). T0OVF is interrupt level IRQ4, vector E2H. T0INT also belongs to interrupt level
IRQ4, but is assigned the separate vector address, E4H.
A timer 0 overflow interrupt pending condition can be cleared by both software and hardware when it has been
serviced.
A timer 0 match/capture interrupt pending condition should be cleared by software when it has been serviced.
Interval Mode (match)
Timer 0 module can generate an interrupt: Timer 0 match interrupt (T0INT).
In interval timer mode, a match signal is generated and T0OUT is toggled when the counter value is identical to
the value written to the T0 reference data register, T0DATAH/L. The match signal generates a timer 0 match
interrupt (T0INT, vector E4H) and clears the counter.
Capture Mode
In capture mode for Timer 0, a signal edge that is detected at the T0CAP pin opens a gate and loads the current
counter value into the T0 data register (T0DATAH/L for rising edge, or falling edge). You can select rising or
falling edges to trigger this operation.
Timer 0 also gives you capture input source, the signal edge at the T0CAP pin. You select the capture input by
setting the capture input selection bit in the port 2 control register, P2CONH,.
Both kinds of timer 0 interrupts (T0OVF, T0INT) can be used in capture mode, the timer 0 overflow interrupt is
generated whenever a counter overflow occurs, the timer 0 capture interrupt is generated whenever the counter
value is loaded into the T0 data register (T0DATAH/L).
By reading the captured data value in T0DATAH/L, and assuming a specific value for the timer 0 clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin.
PWM Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0OUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value
written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter but can
generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then continuous increasing
from 0000H. Whenever an overflow is occurred, an overflow (OVF0) interrupt can be generated.
Although you can use the match or the overflow interrupt in the PWM mode, these interrupts are not typically
used in PWM-type applications. Instead, the pulse at the T0OUT pin is held to low level as long as the reference
data value is less than or equal to the counter value and then the pulse is held to high level for as long as the data
value is greater than the counter value. One pulse width is equal to t
CLK
.