User Manual

CompactFlash Memory Card Interface Description
3-16 CompactFlash
®
Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
ADDR valid
(See note 1)
IORD-/IOWR-
WRITE
DD(7:0)
(See note 2)
READ
DD(7:0)
(See note 2)
t
1
t
2
t
0
t
9
t
2i
t
6
t
4
t
5
t
6z
t
3
1. Device address consists of signals -CS0, -CS1 and -DA(2:0).
2. Data consists of DD(7:0).
3. SanDisk CompactFlash Memory Cards do not assert an -IORDY signal.
4. All signals are shown with the asserted condition facing the top of the page. The negated condition is
shown towards the bottom of the page relative to the asserted condition.
Figure 3-5. Register Transfer To/From Device
Table 3-12. Register Transfer To/From Device
PIO Timing Parameters Mode 4 ns Note
t
0
Cycle time (min) 120 1
t
1
Address valid to IORD-/IOWR- setup (min) 25
t
2
IORD-/IOWR- pulse width 8-bit (min) 70 1
t
2i
IORD-/IOWR- recovery time (min) 25 1
t
3
IOWR- data setup (min) 20
t
4
IOWR- data hold (min) 10
t
5
IORD- data setup (min) 20
t
6
IORD- data hold (min) 5
t
6z
IORD- data tri-state (max) 30 2
t
9
IORD-/IOWR- to address valid hold (min) 10
1. t
0
is the minimum total cycle time, t
2
is the minimum command active time, and t
2i
is the minimum command
recovery time or command inactive time. The actual cycle time equals the sum of the actual command active
time and the actual command inactive time. The three timing requirements of t
0,
t
2
, and t
2i
shall be met. The
minimum total cycle time requirements are greater than the sum of t
2
and t
2i.
This means a host implementation
may lengthen either or both t
2
or t
2i
to ensure that t
0
is equal to or greater than the value reported in the devices
IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.