Product manual

CompactFlash Memory Card Product Manual Preliminary
SanDisk CompactFlash Memory Card Product Manual Rev. 8 © 2001 SANDISK CORPORATION
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4.3.6 Common and Attribute Memory Write Timing
The write timing specifications for Common and
Attribute memory are the same.
Table 4-4 Common and Attribute Memory Write Timing Specifications
600 ns
1,2
250 ns
3
200 ns 150 ns 100 ns Speed Version
Item
Symbol
IEEE
Symbol
Min Max Min Max Min Max Min Max Min Max
Write Cycle Time t
c
W tAVAV 600
2
250
3
200 150 100
Write Pulse Width t
w
(WE) tWLWH 300
2
150
3
120 80 60
Address Setup Time
4
t
su
(A) tAVWL 50 30 20 20 10
Address Setup Time
for WE#
4
t
su
(A-WEH) tAVWH 350
2
180
3
140 100 70
Card Enable Setup
Time for WE#
t
su
(CE-WEH) tELWH 300
2
180
3
140 100 70
Data Setup Time for
WE#
t(D-WEH) tDVWH 150
2
80
3
60 50 40
Data Hold Time t
h
(D) tWMDX 70 30 30 20 15
Write Recover Time t
rec
(WE) tWMAX 70 30 30 20 15
Output Disable Time
from WE#
t
dis
(WE) tWLQZ 150 100 90 75 50
Output Disable Time
from 0E#
t
dis
(OE) tGHQZ 150 100 90 75 50
Output Enable Time
from WE#
t
en
(WE) tWHQNZ 5 5 5 5 5
Output Enable Time
from OE#
t
en
(OE) tGLQNZ 5 5 5 5 5
Output Enable Setup
from WE#
t
su
(OE-WE) tGHWL 35 10 10 10 10
Output Enable Hold
from WE#
t
h
(OE-WE) tWHGL 35 10 10 10 10
Card Enable Setup
Time
5
t
su
(CE) tELWL 0 0 0 0 0
Card Enable Hold
Time
5
t
h
(CE) tGHEH 35 20 20 20 15
WAIT# Valid from
WE#
5
t
v
(WT-WE) tWLWTV 100 35 35 35 35
WAIT# Pulse
Width
6
t
w
(WT) tWTLWTH
12µs 12µs 12µs 12µs 12µs
WE# High from
WAIT# Released
6
t
v
(WT) tWTHWH 0 0 0 0 0
1. 600 ns cycle times apply for 3.3 V operating voltage.
2. 3.3 V timing for cycles >600 ns are equal to value given + (cycle time-600). All other parameters are identical.
3. 5 V timing for cycles >250 ns are equal to value given + (cycle time-250). All other parameters are identical.
4. The REG# signal timing is identical to address signal timing.
5. These timings are specified for hosts and cards which support the WAIT# signal.
6. These timings are specified only when WAIT# is asserted within the cycle.
NOTE: All timings measured at the PC Card. Skews and delays from the system driver/receiver to the PC Card must
accounted for by the system.