User Manual

Introduction to the TriFlash with SD Interface

1.5.7.12. Copy Bit

The content of a TriFlash can be marked as an original or a copy using the copy bit in the CSD register. Once the

Copy bit is set (marked as a copy) it cannot be cleared. The Copy bit of the TriFlash is programmed (during test and

formatting on the manufacturing floor) as a copy. The TriFlash can be purchased with the copy bit set (copy) or

cleared, indicating the TriFlash is a master. This feature is implemented in the TriFlash controller firmware and not

with a physical OTP cell.

1.5.7.13. The CSD Register

All the configuration information of the TriFlash is stored in the CSD register. The MSB bytes of the register

contain manufacturer data and the two least significant bytes contain the host controlled data, the card Copy, write

protection and the user file format indication.

The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and

PROGRAM_CSD commands.

1.5.8. TriFlash—SPI Mode

The SPI mode is a secondary communication protocol for TriFlash devices. This mode is a subset of the SD Bus

protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other

vendors’) microcontrollers.

1.5.8.1. Negotiating Operating Conditions

The operating condition negotiation function of the SD Bus is supported differently in SPI mode by using the

READ_OCR (CMD58) command. The host shall work within the valid voltage range (2.7 to 3.6 volts) of the device

or put the device in an inactive state by sending a GO_INACTIVE command to the device.

1.5.8.2. Card Acquisition and Identification

The host must know the number of devices currently connected on the bus. Specific device selection is done via the

CS signal. The internal pull-up resistor on the CD line may be used for device detection (insertion/removal).

1.5.8.3. Card Status

In SPI mode, only 16 bits (containing the errors relevant to SPI mode) can be read out of the 32-bit TriFlash status

1.5.8.4. Memory Array Partitioning

Memory partitioning in SPI mode is equivalent to SD Bus mode. All read and write commands are byte addressable

with the limitations given in section 1.5.7.5 above.