User Manual

Table Of Contents

MC45 Hardware Interface Description

P R E L I M I N A R Y

MC45_HD_01_V00.02a Page 52 of 90 12.08.2002

Note: Before starting the data transfer the clock SCLK should be available for at least

three cycles.

After the transfer of the LSB0 the clock SCLK should be still available for at least

three cycles.

SLCK

RFSDAI

RXDDAI

(input)

Internal

signal

(input)

Flag

T = 100ns to 5,000 ns

Figure 18: DAI timing on transmit path

SLCK

TFSDAI

TXDDAI

(input)

Internal

signal

(output)

Flag

T = 100ns to 5,000 ns

Figure 19: DAI timing on receive path