Data Sheet

Time
DEBUG_CLK
P2_2
t
1
t
2
1/f
clk_dbg
T0436-01
T0479-01
SCK
SSN
MOSI
MISO
D0
D1
X
D0
X
t
2
t
3
X
t
8
t
10
t
11
t
9
CC2541
SWRS110D –JANUARY 2012–REVISED JUNE 2013 www.ti.com
Figure 4. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
clk_dbg
Debug clock frequency (see Figure 5) 12 MHz
t
1
Allowed high pulse on clock (see Figure 5) 35 ns
t
2
Allowed low pulse on clock (see Figure 5) 35 ns
EXT_RESET_N low to first falling edge on debug clock (see
t
3
167 ns
Figure 7)
t
4
Falling edge on clock to EXT_RESET_N high (see Figure 7) 83 ns
t
5
EXT_RESET_N high to first debug command (see Figure 7) 83 ns
t
6
Debug data setup (see Figure 6) 2 ns
t
7
Debug data hold (see Figure 6) 4 ns
t
8
Clock-to-data delay (see Figure 6) Load = 10 pF 30 ns
Figure 5. Debug Clock – Basic Timing
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