rsit Un ive ert fH yo for dsh ire
ire Abstract The Motorola MC68000 family of microprocessors is now widely recognised as an industry dsh standard for industrial control and multi-user computer systems requiring the speed and power of an advanced 16/32-bit microprocessor. The IDE interface is now mostly used in personal computer. Therefore, the project, which combined the two technologies, will have for potential.
ire dsh for Acknowledgements The author wishes to thank a number of people who have contributed help and assistance during the project. Special thanks are extended to David Meads, whom as project supervisor ert provided support and guidance throughout the project. fH The following people offered the support and advice throughout the project development phase. yo Mr. Tony Crook helped and advised all the source components. Mr.
ire dsh for GND Register Ground fH REG ert Glossary Integrated Drive Electronics 68K MC68000 FAT File Allocation Table PIO Port Input/Output HDD rsit yo IDE Direct Memory Access CHS Cylinder Head Sector LBA Logical Block Addressing Un ive DMA VFAT Virtual File Allocation Table NTFS New Technology File System HPFS High Performance File System PGCR Port General Control Register PADDR Port A Data Direction Register Hard disk
PCDDR Port C Data Direction Register PBCR Port B Control Register PADR Port A Data Register PBDR Port B Data Register PCDR Port C Data Register for Port A Control Register Un ive rsit yo fH ert PACR ire Port B Data Direction Register dsh PBDDR
ire CONTENTS Abstract.........................................................................................................................i dsh Acknowledgements...................................................................................................ii Glossary…..................................................................................................................iii for Contents ....................................................................................................
ire III MC68000, VME Bus and Flite 68K Introduction.....................................13 3.1 VME Introduction[10]..........................................................................................13 3.1.1 Arbitration Bus........................................................................................14 dsh 3.1.2 Data Transfer Bus………………………………………………………14 3.1.3 Priority Interrupt Bus………………………………………………...…14 3.1.4 Utility Bus ……………………………………………………………..15 for 3.
ire 4.3 The Difference between FAT12/16 and FAT32………………………………24 4.4 Other Technologies…………………………………………………………..26 dsh 4.4.1 VFAT (Virtual File Allocation Table)…………………………………26 4.4.2 NTFS (New Technology File System)…………………………………26 for 4.4.3 HPFS (High Performance File System)………………………………..27 V Hardware Interface Design...............................................................................28 ert 5.1 General Concept …………………………………………………...……….. 28 5.2 I/O Chip Selections…………………………………………………………..
6.5 IDE Command Routine………………………………………………………46 ire 6.5.1 PIO Data Read Commands[7]……………………………………..…...46 6.5.2 PIO Data Write Routine[7]…………………………….……………….47 dsh 6.5.3 System Running Routine………………………………………………49 VII Testing and Analysis.......................................................................................50 7.1 Introduction of Achieved Aspects in Testing………………………………50 for 7.2 Phase 1: Hardware Analysis………………………………………………..50 7.3 Phase 2: Software Test……………………………………………………..50 ert 7.
Appendix B-3 Flite 68K DUART&PI/T Architecture………………………………...B ire Appendix B-4 MC68230 Peripheral Interface/Timer(PI/T)...………………………...B Appendix C-1 74HC245 Data Sheet………………………………………………….C dsh Appendix C-2 74HC245 Data Sheet………………………………………….………C Appendix C-3 74HC245 Data Sheet…………………………………………….……C Appendix D Circuit Diagram……………………………………………...………….D Appendix E-1 Source Code ……………………………………………...……..…….E for Appendix E-2 Source Code……………………………………………....……..…….
ire Figure 8.2 Future Mode of the Project-2……………………………………………..55 Tables dsh Table 2.1 ATA PIO Modes…………………………………………………………….7 Table 2.2 Formatted Capacity of ST32122A………………………………………...11 Table 2.3 Default Logical Geometry of ST32122A………………………………….11 for Table 3.1 Integer Data Formats………………………………………………………18 Table 3.2 Asynchronous Bus Control………………………………………………..20 Table 3.3 Function Code Outputs…………………………………………………....21 ert Table 5.1 Hardware Component Used In Project……………………………………28 Table 6.
having a separate controller. This reduces cost and also makes firmware updates easier since ire there is no cross-manufacturer complexity. The application environment for the AT dsh Attachment Interface is any computer which uses an AT Bus or 40-pin ATA interface. Most drives today are IDE. These drives have the controller built on. They plug into a bus connector on the motherboard or an adapter card. Such drives are easy to install and require a minimum number of cables.
To achieve the project aims, an organised work schedule was required. Planning all the ire various stages of the project and placing them into a Gantt chart, details can be found in Appendix G; this gave a chronological sequence of the activities that needed to take place, dsh which gave a good illustration of the time management required.
The report is laid out in a logical order, with the first few chapters providing relevant ire background information on the MC68000 and IDE technology. Brief explanations of dsh chapter content are provided below: Chapter II: IDE and ST32122A Introduction In this chapter the IDE technology is briefly discussed, this includes information on the IDE for history and types.
The prototype interface will be tested and the results and waveforms from the testing phase ire are discussed in this chapter. Problems encountered in the testing phase are also dsh documented here. Chapter VIII: Further Development This chapter contains details of development that may possible future enhancements in the for project..
2.1 The Original IDE/ATA ire The first IDE interface was created by CDC, Compaq, and Western Digital. They used 40pin connector. They were large drives of the 5.25" form, but were only 40M. It is used in dsh the early Compaq 386 systems, using WD controllers. Later, Compaq founded Conner. Conner produced drives for Compaq, but was later sold. In the late 1980's, the ATA IDE was set as ANSI standard. This caused all manufacturers’ to agree with a common design for for the interface.
ire dsh Host adapter Microprocessor Drive con trol electronics for IDE inte rfa ce Formatter Data Data Separator Buffer Controller fH 2.2 ATA I/O: Dual Drives ert Figure 2.1 IDE Block Diagram ATA has the ability to operate two drives together in a chain. The primary drive is the master, and the second drive is the slave. On most drives, a master or a slave jumper was set yo on the drive itself. When two drives are on the same ribbon cable, all commands are received by both controllers.
are capable of using translation modes, thereby using different geometry when talking ire with the drive than when talking with the software. The BIOS produced dated around dsh 1994 or later probably enhanced. Faster Data Transfer ATA-2 offers several different modes for higher performance. Most drives today are capable of PIO Modes 3 and 4, which are very fast. PIO (Programmed I/O) modes for determine the speed at which data is transferred to and from the drive.
If it sees something that indicates a problem, it is capable of notifying the user (or, if ire applicable, system administrator). dsh In essence, SMART is merely a set of software tools on the drive itself, constantly running diagnostics. They run diagnostics on the motors, the media, the electronic components, and the mechanical components.
Cable configuration is quite simple with the ATA IDE interface. There is a single cable with ire three connectors on it. One of these connectors plugs into the IDE connector on the motherboard or I/O adapter card. The other two attach to the drives. On most setups, one dsh end of the cable is attached to the IDE controller. The middle connector attaches to the secondary drive, if there is one. The other end is attached to the primary drive, or drive C:.
ire HOST s yst em dsh Host bus for Host adapt er Slave Drive (Drive 1) ert M aster Drive (Drive 0) fH Figure 2.2 IDE Configurations for AT Compatibles 2.6 Seagate ST32122A Introduction 2.6.1 General Introduction yo The Medalist 2122 (ST32122A), provide the following key features: · Low power consumption · Quiet operation rsit · Support for S.M.A.R.T. drive monitoring and reporting · High instantaneous (burst) data-transfer rates (up to 33.
ST32122A 2,111 4,124, 736 512 ST32122A Cylinders Read/Write Heads dsh CHS Mode ire Table 2.2 Formatted Capacity of ST32122A 4,092 16 Sectors per track 63 for Table 2.3 Default Logical Geometry of ST32122A 2.6.2 Master/Slave Configuration A master/slave relationship can be established between two drives that are attached to a ert single AT bus. A drive to be configured a master or slave by setting the master/slave fH jumpers, shown in Figure 2.3.
ire dsh for ert fH yo Figure 2.3 Alternate Capacity Jumper and Master/Slave Jumpers rsit Since the project will only use one drive, the jumper was set to master and the relevant pins Un ive are also set. The details will be given out in chapter IV.
III MC68000, VME Bus and Flite 68K Introduction ire In this chapter the general concept of VME bus, MC68000 and FLT-68k will be introduced. dsh 3.1 VME Introduction VME bus (Versa Module Europa) is a flexible open-ended bus system which makes use of the Eurocard standard. It was introduced by Motorola, Phillips, Thompson, and Mostek in for 1981.
A module controlling the bus will drive the bus busy line (BBSY) low to show that it is in ire use. When this line is not low the arbiter module will sample the bus request lines (BR0BR3) looking for a pending action. Requests on BR3 have the highest priority. Requests of dsh equal priority are handled by a daisy chain using the bus grant in lines (BG0IN-BG3IN) and the bus grant out lines (BG0OUT-BG3OUT).
Power is supplied to modules via pins at +5 V, -12 V and +12 V. An optional battery ire backup of the +5 V supply (+5STDBY) can also be present. The utility bus supports an independent 16 MHz system clock (SYSCLK). The system failure line (SYSFAIL) and AC dsh failure line (ACFAIL) are bussed lines used to indicate global problems. The system reset line (SYSRESET) is used for initialization.
ire dsh for ert fH Figure 3.1 MC68000 User Programming Model yo 3.2.1.1 Data Registers (D7 – D0) These registers are for bit and bit field (1 – 32 bits), byte (8 bits), word (16 bits), long-word rsit (32 bits), and quad-word (64 bits) operations. They also can be used as index registers. 3.2.1.2 Address Registers (A7 – A0) These registers can be used as software stack pointers, index registers, or base address Un ive registers.
places a new value in the PC. For some addressing modes, the PC can be used as a pointer ire for PC relative addressing. dsh 3.2.1.4 Condition Code Register Consisting of five bits, the CCR, the status register’s lower byte, is the only portion of the status register (SR) available in the user mode. Many integer instructions affect the CCR, indicating the instruction’s result. Program and system control instructions also use certain for combinations of these bits to control program and system flow.
Set if the most significant bit of the result is set; otherwise clear. Z—Zero dsh Set if the result equals zero; otherwise clear. ire N—Negative V—Overflow Set if an arithmetic overflow occurs implying that the result cannot be represented in the C—Carry for operand size; otherwise clear. Set if a carry out of the most significant bit of the operand occurs for an addition, or if a ert borrow occurs in a subtraction; otherwise clear. 3.2.1.
The input and output signals of MC68000 can be roughly divided into five parts: address ire bus, data bus, processor status block, control block and the clock part. The block diagram is fH ert for dsh shown as below: Figure 3.3 MC68000 Input and Output Signals yo 3.2.2.1 Address Bus (A23–A1) This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
Asynchronous data transfers are controlled by the following signals: address strobe, ire read/write, upper and lower data strobes, and data transfer acknowledge. The detail of pins ert for dsh set is show in table 3.2 3.2.2.4 Bus Arbitration Control fH Table 3.2 Asynchronous Bus Control yo The bus request, bus grant, and bus grant acknowledge signals form a bus arbitration circuit to determine which device becomes the bus master device. rsit 3.2.2.
The system control inputs are used to reset the processor, to halt the processor, and to signal ire a bus error to the processor. The outputs reset the external devices in the system and signal a dsh processor error halt to those devices. 3. 2.2.7 MC68000 Peripheral Control These control signals are used to interface the asynchronous M68000 processors with the for synchronous MC68000 peripheral devices. 3.2.2.
Power is supplied to the processor using these connections. The positive output of the ire power supply is connected to the VCC pins and ground is connected to the GND pins. dsh 3.3 Flite 68k Training System Introduction The develop board used in the project was Flite FLT-68K 68000 Microprocessor Training System. The original package is designed to provide the introduction to 16/32-bit for microprocessors by way of the very popular Motorola MC68000.
can accept various types of memory, EPROM or RAM, expanding the total system RAM- ire up to 512K bytes. The power requirements of the FLIGHT-68K are simply an unregulated 9 volt DC supply capable of delivering 700mA. The various voltages required by the system dsh are derived from this on the card. A 9 Volt 1 Amp mains adapter is supplied with the system. A picture of Flt-68 is shown in the Appendix A.
The FAT is a roadmap, or index, those points to the location where all the information in system uses it to store and retrieve files containing information. dsh 4.2 History of FAT Table ire files is stored on a floppy disk or hard drive. The FAT is extremely important because the The existing File Allocation Table (FAT) file system was invented in 1977 as a way to store for data on floppy disks for Microsoft stand-alone Disk Basic.
NTFS but windows is faster if confined to a small area. FAT performance drops off after ire 400mb's on up. FAT32 will not recognise FAT or NTFS volumes of other operating systems--so you dsh can't use them. It supports drives up to 2 terabytes. It uses smaller clusters (e.g. 4k clusters up to 8 gigs). for Fat12/16 and Fat32 is a Partition size/cluster size issue. FAT32 solves this problem by reducing to 4KB the default file cluster size for partitions between 260MB and 8GB.
FAT32X is a form of FAT32 created by the Windows Fdisk utility when partitions over Allocation Table is moved to the end of the disk in these cases. ire 8 GB in size are created, and the 1024 cylinder threshold of the disk is passed. The File dsh On most standard IDE drives (SCSI are different but similar rules apply) it is normal to have 16 heads and 63 sectors per track. Cylinders increase as drive size increases.
This system sorts the directory based on names and is better organized, is faster and is a ire better space saver. It allocates data to sectors instead of clusters, organized into 8mb bands. This banding improves performance because the read/write heads don't have to return to NetWare File System: This is quick because Novell dsh track zero each time for access. developed it for NetWare servers being NetWare 3.x and 4.x partitions.
At last the details of the connection of the IDE I/O adapter card will be given. The circuit ire diagram of the adapter is in the Appendix D. dsh Before the presentation in November the hard disk was thought to be connected directly to the Flite board. However, in the presentation teachers gave the advice that the hard disk can not connect to the Flite 68K directly, because the high volute of the hard disk will burn up the Flite board. Thus two I/O chip were chosen to build up an I/O adapter card.
receive directions. The “245” features an output enable (OE) input for easy cascading and a ire send/receive (DIR) for direction control. OE controls the outputs so that the buses are dsh effectively isolated. The data sheet of 74HC245 is shown in Appendix C 5.3 IDE Configurations 5.3.
ire dsh for ert fH yo rsit Figure5.1 IDE Physical Interface 5.3.2 Signal Descriptions CS1FX- (Drive Chip Select 0) Un ive This is the chip select signal decoded from the host address bus used to select the Command Block Registers. CS3FX- (Drive Chip Select 1) This is the chip select signal decoded from the host address bus used to select the Control Block Registers.
This is the 3-bit binary coded address asserted by the host to access a register or data port in DASP- (Drive Active/Drive 1 Present) dsh ire the drive. This is a time-multiplexed signal which indicates that a drive is active, or that Drive 1 is present. This signal shall be an open collector output and each drive shall have a 10K ohm for pull-up resistor. DD0-DD15 (Drive Data Bus) ert This is an 8- or 16-bit bidirectional data bus between the host and the drive.
- The host writing the Command Register or ire - The host reading the Status Register NOTE: Some drives may negate INTRQ on a PIO data transfer completion, except on a dsh single sector read or on the last sector of a multi-sector read. On PIO transfers, INTRQ is asserted at the beginning of each data block to be transferred. A data block is typically a single sector, except when declared otherwise by use of the Set multiple commands.
ire Optional group There are also some optional pins on the interface and the project did not use them. dsh They were left to high impedance state and are listed below: Pin 29, DMACK- (DMA Acknowledge) and pin 21, DMARQ (DMA Request). Because DMA technology was not used in the project, Pin 27 IORDY (I/O Channel Ready), pin 34 PDIAG- (Passed Diagnostics) and pin 28 CSEL (Spindle for Synchronization/Cable Select), for there is only one hard disk.
handshake pins provide an interface flexible enough for connection to a wide variety of low, ire medium, or high speed peripheral or other computer systems. The PI/T ports allow use of vectored or auto vectored interrupts, and also provide a DMA request pin for connection to dsh the MC68450 direct memory access controller (DMAC) or a similar circuit. The PI/T timer contains a 24 bit wide counter and a 5-bit prescaler can be used.
In this project Port A was used to transfer data, which was bidirectional. Port B was used to ire control the control block on the IDE interface. Port C was used to control the two I/O chips. dsh 5.5 IDE I/O Adapt Manufacture The details of pin connecting and function will be introduced here. However, a clearer circuit diagram will be shown in Appendix D. The first 74HC245 was used to transfer data, for which is bidirectional.
Switc ire Reset dsh +5vol 0 Un ive rsit yo fH ert for Figure 5.
In this chapter the logical configuration of MC68230 will be introduced first and then the code and details of the command of IDE is in the Appendix E. dsh 6.1 Logical Configuration of MC68230 ire IDE logical configuration. At last the flow of the software will be explained.
Control Register (PGCR) Port A Data Direction Register (PADDR) Port B Data Direction Register (PBDDR) Port C Data Direction Register (PCDDR) Port A Control Register (PACR) handshaking signals (H1, H2, H3 and H4) 04 Selection of individual port bits as inputs or outputs 800007 06 Selection of individual port bits as inputs or outputs 800009 08 Selection of individual port bits as inputs or outputs 80000D 0C Selection of port sub-modes and handshake signals operation Port B Control Register (PBCR)
Figure 6.1 shows the structure of the PGCR. In this project, the port used mode 00 and the for dsh ire H12, H34 were disabled. Therefore, the value of the PGCR register was 00h. Figure 6.
ire dsh Figure 6.2 Structure of PXDDR(X=A, B, C). for 6.3 MC68230 Mode Selection and PACR, PBCR Configuration The port A control register, in conjunction with the programmed mode and the port B PACR7-PACR6 Specify the port A submode fH PACR5-PACR3 ert submode, controls the operation of port A and the handshake pins H1 and H2. Control the operation of the H2 handshake pin and the H2S status bit; PACR2 yo Determines whether an interrupt will be generated when the H2S status bit goes to one.
ire dsh for 6.4 IDE I/O Register Descriptions ert Figure 6.3 PACR Configuration for Mode 0, Submode 00 Communication to or from the drive is through an I/O Register that routes the input or fH output data to or from registers (selected) by a code on signals from the host (CS1FX-, CS3FX-, DA2, DA1, DA0, DIOR- and DIOW-). Thus the project followed the same routine. The I/O register of the IDE interface can be divided in two groups: Command Block yo Registers and Control Block Registers.
1 0 X N A 1 1 0 N A 1 1 1 Not used XXh ire A Device Control Not used XXh 2Eh XXh 3Eh XXh Data 21h 41h dsh N impe. Data bus high impe.
ire If this register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors which need to be dsh transferred in order to complete the request. The contents of this register may be defined otherwise on some commands e.g. Initialize for Drive Parameters, Format Track or Write same commands. Sector Number Register ert This register contains the starting sector number for any disk data access for the subsequent command.
ire Register is updated to reflect the current LBA Bits 16-23. Drive/Head Register dsh This register contains the drive and head numbers. The contents of this register define the number of heads minus 1, when executing an Initialize Drive Parameters command. At command completion, these bits are updated to reflect the current LBA bits 24-27. for Data Register This 16-bit register is used to transfer data blocks between the device data Buffer and the ert host.
- BSY (Busy) is set whenever the drive has access to the Command Block Registers. The BSY=1. When BSY=1, a read ire host should not access the Command Block Register when of any Command Block Register shall return the contents of the Status Register. This bit dsh is set by the drive (which may be able to respond at times when the media cannot be accessed) under the following circumstances: a) Within 400 nsec after the negation of RESET- or after SRST has been set Device Control Register.
- IDX (Index) is set once per disk revolution. ire - ERR (Error) indicates that an error occurred during execution of the previous command. dsh The bits in the Error Register have additional information regarding the cause of the error. 6.5 IDE Command Routine For all commands, the host first checks if BSY=1, and should proceed no further unless and for until BSY=0. For most commands, the host will also wait for DRDY=1 before proceeding. Those commands shown with DRDY=x can be executed when DRDY=0.
the programmer and the drive level which interface the hard disk. Drive Level dsh Program Level ire The following picture shows PIO Read Routine on both the program level which interface BSY=0 Issue Command DRDY=1 BSY=1 for Setup DRQ=1 BSY=0 Assert INTRQ ert Read Status Reg Transfer data End fH Negative INTRQ DRQ=0 BSY=1 yo Figure 6.4 IDE PIO Data Read Routine 6.5.
f) When the drive has completed processing of the sector, it clears BSY and asserts g) After detecting INTRQ, the host reads the Status Register. dsh h) The drive clears the interrupt. ire INTRQ. If transfer of another sector is required, the drive also sets DRQ. i) If transfer of another sector is required, the above sequence is repeated from d).
6.5.3 System Running Routine ire The program of the project was very easy. It implemented data transfer between hard disk and the Flite 68K in the FAT table. Port was initialised after the code ran. Then it read the dsh specific sector of the FAT table and writes back to another empty, which was indicated in advance. The address of the two values was given in the program. The value of them can be Start ert Read data to REG for modified. fH Write data to HDD yo END Figure 6.
Vero board of the adapter card was built in the following week. Fortunately, the hardware ire worked perfectly and all the connections did not have any short circuit. All the components passed the test only once because every pin was carefully checked twice and the short dsh circuit was also carefully checked soon after each pin each finished. 7.3 Phase 2: Software Test for The problems came from the software testing. Nevertheless, they were small problems except one.
ire dsh for ert fH yo rsit VIII Further Development Since the hardware works well, the future work may focus on the software of the prototype. Un ive For example fully control the FAT table. 8.1 FAT Table Practically Introduction DOS keeps track of its used, unused, and damaged sectors by using a table called the file allocation table (FAT). The FAT is always the second and third sectors of a disk. The FAT keeps track of all of the sectors on a disk.
ire DOS groups disk sectors into collections of multiple sectors called clusters. The FAT records clusters as opposed to sectors. For each cluster on the disk, DOS places one of the dsh values shown in Table 8.1. DOS allocates disk space to the file a cluster at a time. By keeping track of which clusters a file uses, DOS in essence creates a chain of sectors that you can follow one right for after another, to locate the contents of a file.
ire Table 8.2 Entry in Directory Structure Each disk type sets aside a different amount of space for root directory entries. Table 8.3 Directory Entries Single-sided 4 Double-sided 7 Quad-density 14 Fixed disk 32 Directory dsh Disk Type Sectors 64 112 for 224 512 summarizes the number of files that each disk type can place in the root directory. ert Table 8.
Read Write dsh Read or Write ire Port Initialise for Read Data to REG Write Data to HDD ert Read Data to REG Figure 8.1 Future Mode of the Project-1 fH The host can transfer the data manual and specifically. yo Start rsit What do you want to do? Delete file on the slave hard Un ive Copy file on the slave hard Copy file from the host pc End Figure 8.2 Future Mode of the Project-2 The hard disk can transfer the data both form the hard disk of the host PC or from itself.
ire dsh for ert fH yo IX Conclusions 9.1 Research, Seminar and Project Management The aim of the project was to develop an interfacing circuit, between the Motorola m68000 rsit boards and the IDE controller. In the beginning, a lot of time was spent on how the VME bus works. However, it now seemed is not very important to the project. After that understanding the MC68000 was focused on.
9.2 Design and Implementation ire In this stage, several different I/O chip had been changed to meet the requirement of the project from unidirectional to bidirectional. Although much time had been spend on weld dsh the Vero board and check the short circuit, it is very worth because the following hardware testing and software did not occur any big problem cause of the design and weld. for 9.3 Software Code Software of the project is not as complex as the hardware.
estimated that the hardware implement phase would take quite so long, this meant that time ire restrictions didn’t permit the programming of project goes long and less FAT technology dsh will used in the project. The picture of the prototype of the MC68000-IDE Interface is shown in Appendix F. for Reference ert [1] Bacon, J (1986) The Motorola MC68000: An Introduction to Processor, Memory and Interfacing UK: Prentice Hall. fH [2] Coates.R.
http://www.hardwarecentral.com/hardwarecentral/tutorials/39/1/ dsh [10]AN INTRODUCTION TO VME http://www http://wwwesd.fnal.gov/esd/catalog/intro/introvme.htm http://www.systweak.com/fat32/fat1.htm ert [12] Seagate Product Manual 1998 for [11]Fat32 & File System Guide ire [9]IDE Interface Introduction fH Bibliography Bramer, B (1991) MC68000 Assembly Language Programming UK: Edward Arnold.
Motorola (1984) M68000: 16/32-BIT Microprocessor Programmer's Reference Manual UK: ire Prentice-Hall. dsh Schmidt, F (1991) SCSI Bus and IDE Interface: Protocols, Applications and Programming UK: Carmel, Inc. Un ive rsit yo fH ert for DeVoney, C (1987) MS-DOS User's Guide Edition USA: Indianapolis, Inc.
ire Appendix Un ive rsit yo fH ert for dsh Appendix A Flite FLT-68K 68000 Microprocessor Training System
rsit Un ive ert fH yo for dsh ire
rsit Un ive ert fH yo for dsh ire
rsit Un ive ert fH yo for dsh ire
Un ive rsit yo fH ert for dsh ire Appendix B-4 MC68230 Peripheral Interface/Timer(PI/T)
Un ive rsit yo fH ert for dsh ire Appendix C-1 74HC245 Data Sheet
Un ive rsit yo fH ert for dsh ire Appendix C-2 74HC245 Data Sheet Appendix C-3 74HC245 Data Sheet
ire dsh for ert fH yo rsit Un ive Appendix D Circuit Diagram
ire +5V DD8 DD7 DD9 DD6 DD10 DD5 DD11 DD4 DD12 DD3 DD13 DD2 DD14 DD1 DD15 DD0 Keypin GND GND DMARQ GND DIOW- GND DIOR- CSEL IORDY GND DMACK- ert DIR Vcc A0 OEA1 B0 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 74HC245 PDIAG- DA1 DA0 DASP- yo CS3FX- CS1FXGND +5v PB0 PC0 PB1 PC1 PB2 PC3/TOUT PB3 PC4 PB4 PC5/PIPQ PB5 PA7 PB6 PA6 PB7 PA5 N.C. PA4 GND GND PC2/TIN PA3 H4 PA2 H3 PA1 H2 PA0 H1 N.C. PC6/PIACK N.C PC7/TIACK N.C. N.C. N.C. N.C. N.C. N.C.
// Port B Control Reg Address*/ char *PADDRTR = 0x800005; // Port A Data Direction Reg Address */ char *PBCRTR = 0x80000F; // Port B Control Reg Address*/ char *PBDDRTR = 0x800007; ire char *PACRTR = 0x80000D; // Port B Data Direction Reg Address*/ // Port A Data Reg Address*/ char *PBDRTR = 0x800013; // Port B Data Reg Address*/ char *PCDDRTR = 0x800009; // Port C Data Direction Reg Address*/ dsh char *PADRTR = 0x800011; // Port C Data Reg Address*/ char *PGCRTR= 0x800001; // Port General
PADR=0x01; //enable 8-bit data tansfer// PBDR=0x49; //write to sector count// PADR=0x01; //sector count is 1, indicates transfer 1 sector// PBDR=0x59; //WRITE TO LBA bits 0-7// PADR=0x01; //sector 1// PBDR=0x45; //WRITE TO LBA bits 8-15// PADR=0x00; //cylinder 0// PBDR=0x55; //WRITE TO LBA bits 16-23// PBDR=0x4D; //WRITE TO LBA bits 24-27// PADR=0x00; //head 0// PBDR=0x5D; //write to command register// PADR=0x20; //read sector command// PCDR=0x02; //enable 2 chip a->b read// //port
PBDR=0x51; //set feature register// PADR=0x01; //enable 8-bit data tansfer// PBDR=0x49; //write to sector count// PADR=0x01; //sector count is 1, indicates transfer 1 sector// PBDR=0x59; //WRITE TO LBA bits 0-7// PADR=0x3F; //sector 1// PBDR=0x45; //WRITE TO LBA bits 8-15// PADR=0x00; //cylinder 0// PBDR=0x55; //WRITE TO LBA bits 16-23// PADR=0x00; //cylinder 00// PBDR=0x4D; //WRITE TO LBA bits 24-27// PADR=0x00; //head 0// PBDR=0x5D; //write to command register// PADR=0x30; //wri
PBCR=0x00; //Set Port B in submode 00*/ // Set Port C as output*/ ire PCDDR=0xFF; } dsh main() { char D0; char BSY; Read(); // Initialize the Ports// //Run Read routin// printf("%d",BSY); Write(); // Verfiry the transfer completed// // Run Write routin// printf("%d",BSY); ert init(); for char D1; // Verfiry the transfer completed// fH } Appendix F Prototype Picture of the Project Un ive rsit yo Picture of I/O Adapter Card Picture of Prototype System
ire dsh for fH ert Un ive rsit yo Appendix G Project Time Table
rsit Un ive ert fH yo for dsh ire
