Datasheet

DocID023312 Rev 2 19/52
LSM303D Application hints
52
5 Application hints
Figure 5. LSM303D electrical connections
5.1 External capacitors
The C
1
and C
2
external capacitors should be low SR value ceramic type construction (typ.
recommended value 200 m). Reservoir capacitor C
1
is nominally 4.7 μF in capacitance,
with the set/reset capacitor C
2
nominally 0.22 μF in capacitance.
The device core is supplied through the Vdd line. Power supply decoupling capacitors
(C
4
= 100 nF ceramic, C
3
= 10 μF Al) should be placed as near as possible to the supply pin
of the device (common design practice). All the voltage and ground supplies must be
present at the same time to have proper behavior of the IC (refer to Figure 5).
The functionality of the device and the measured acceleration/magnetic field data is
selectable and accessible through the I
2
C/SPI interfaces.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be
completely programmed by the user through the I
2
C/SPI interfaces.
5.2 Pull-up resistors
If an I
2
C interface is used, pull-up resistors (recommended value 10 k) must be placed on
the two I
2
C bus lines.
CS
C
3
= 10µF
Vdd
C
4
= 100nF
GND
Vdd_IO
SDO/SA0
SDA/SDI/SDO
INT 1
SCL/SPC
Digital signal from/to signal controller. Signal levels are defined by proper selection of Vdd_IO
1
5
8
13
TOP VIEW
6
9
1416
9
5
INT 2
C
1
= 4.7µF
C
2
=0.22µF
AM12678V1