Datasheet

DocID023312 Rev 2 21/52
LSM303D Digital interfaces
52
6 Digital interfaces
The registers embedded in the LSM303D may be accessed through both the I
2
C and SPI
serial interfaces. The latter may be SW-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I
2
C interface, the
CS line must be tied high (i.e connected to Vdd_IO).
6.1 I
2
C serial interface
The LSM303D I
2
C is a bus slave. The I
2
C is employed to write data into registers whose
content can also be read back.
The relevant I
2
C terminology is given in the table below.
There are two signals associated with the I
2
C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both lines are high.
The I
2
C interface is compliant with fast mode (400 kHz) I
2
C standards as well as with
normal mode.
Table 9. Serial interface pin description
Pin name Pin description
CS
I
2
C/SPI mode selection (1: SPI idle mode / I
2
C communication enabled; 0: SPI
communication mode / I
2
C disabled)
SCL/SPC
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
SDA/SDI/SDO
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SDO/SA0
SPI serial data output (SDO)
I
2
C less significant bit of the device address (SA0)
Table 10. I
2
C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master