Datasheet

DocID023312 Rev 2 35/52

LSM303D Register description

AODR [3:0] is used to set power mode and ODR selection. In the following table bit

selection of AODR [3:0] for all frequencies is shown.

8.18 CTRL2 (21h)

Table 36. Acceleration data rate configuration

AODR3 AODR2 AODR1 AODR0 Power mode and ODR selection

0 0 0 0 Power-down mode

0 0 0 1 3.125 Hz

0 0 1 0 6.25 Hz

0 0 1 1 12.5 Hz

0 1 0 0 25 Hz

0 1 0 1 50 Hz

0 1 1 0 100 Hz

0 1 1 1 200 Hz

1 0 0 0 400 Hz

1 0 0 1 800 Hz

1 0 1 0 1600 Hz

Table 37. CTRL2 register

ABW1 ABW0 AFS2 AFS1 AFS0 0

(1)

1. This bit must be set to ‘0’ for correct operation of the device.

AST SIM

Table 38. CTRL2 register description

ABW[1:0] Accelerometer anti-alias filter bandwidth. Default value: 00

Refer to Table 39

AFS[2:0] Acceleration full-scale selection. Default value: 000

Refer to Table 40

AST Acceleration self-test enable. Default value: 0

(0: self-test disabled; 1: self-test enabled)

SIM SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

Table 39. Acceleration anti-alias filter bandwidth

ABW1 ABW0 Anti-alias filter bandwidth

0 0 773 Hz

0 1 194 Hz