Datasheet

DocID023312 Rev 2 43/52
LSM303D Register description
52
Reading at this address clears the IG_SRC1 (31h) IA bit (and the interrupt signal on the
corresponding interrupt pin) and allows the refreshment of data in the IG_SRC1 (31h)
register if the latched option was chosen.
8.32 IG_THS1 (32h)
8.33 IG_DUR1 (33h)
The D6 - D0 bits set the minimum duration of the interrupt 1 event to be recognized.
Duration steps and maximum values depend on the ODR chosen.
Table 66. IG_SRC1 register description
IA
Interrupt status. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt; 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt; 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt; 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt; 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt; 1: X low event has occurred)
Table 67. IG_THS1 register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 68. IG_THS1 register description
THS[6:0] Interrupt generator 1 threshold. Default value: 000 0000
Table 69. IG1_DUR1 register
0 D6D5D4D3D2D1D0
Table 70. IG1_DUR1 register description
D[6:0] Duration value. Default value: 000 0000