Document Number: MMA8452Q Rev. 10, 04/2016 NXP Semiconductors Data sheet: Technical data MMA8452Q, 3-axis, 12-bit/8-bit digital accelerometer MMA8452Q The MMA8452Q is a smart, low-power, three-axis, capacitive, micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins.
Contents 1 2 3 4 5 6 7 8 9 Block Diagram and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Block Diagram and Pin Description Internal OSC X-axis Transducer VDD VDDIO INT2 Embedded DSP Functions 12-bit ADC C to V Converter Y-axis Transducer VSS INT1 Clock GEN I2 C SDA SCL Z-axis Transducer Transient Detection (i.e.
Figure 3 shows the device configuration in the six different orientation modes. These orientations are defined as the following: PU = portrait up, LR = landscape right, PD = portrait down, LL = landscape left, back and front side views. There are several registers to configure the orientation detection and are described in detail in the register setting section.
Table 1. Pin descriptions Pin # Pin name Description 1 VDDIO 2 BYP Bypass capacitor (0.1 μF) 3 DNC Do not connect to anything, leave pin isolated and floating. 4 SCL I2C serial clock, open drain 5 GND Connect to ground 6 SDA I2C serial data 7 SA0 I2C least significant bit of the device I2C address, I2C 7-bit address = 0x1C (SA0 = 0), 0x1D (SA0 = 1).
2 Mechanical and Electrical Specifications 2.1 Mechanical characteristics Table 2. Mechanical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25 °C unless otherwise noted. Parameter Test conditions Symbol Min Typ Max — ±2 — — ±4 — FS[1:0] set to 10 8 g mode — ±8 — FS[1:0] set to 00 2 g mode — 1024 — — 512 — — 256 — — ±2.
2.2 Electrical characteristics Table 3. Electrical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25 °C unless otherwise noted. Parameter Supply voltage Interface supply voltage Test conditions Symbol Min Typ Max Unit — VDD(1) 1.95 2.5 3.6 V — VDDIO(1) 1.62 1.8 3.6 V ODR = 1.56 Hz — 6 — ODR = 6.25 Hz — 6 — ODR = 12.5 Hz — 6 — — 14 — — 24 — ODR = 200 Hz — 44 — ODR = 400 Hz — 85 — ODR = 800 Hz — 165 — ODR = 1.56 Hz — 24 — ODR = 6.
2.3 I2C interface characteristics Table 4. I2C slave timing values(1) I2C fast-mode Parameter Unit Symbol Min Max SCL clock frequency fSCL 0 400 kHz Bus-free time between stop and start condition tBUF 1.3 — μs (Repeated) start hold time tHD;STA 0.6 — μs Repeated start setup time tSU;STA 0.6 — μs Stop condition setup time tSU;STO 0.6 — μs μs SDA data hold time tHD;DAT 0.05 0.9(2) SDA setup time tSU;DAT 100 — ns SCL clock low time tLOW 1.
VIL = 0.3VDD VIH = 0.7VDD Figure 5. I2C slave timing diagram 2.4 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum ratings Rating Symbol Value Unit Maximum acceleration (all axes, 100 μs) gmax 5,000 g Supply voltage VDD –0.3 to + 3.6 V Vin –0.3 to VDDIO + 0.3 V Drop test Ddrop 1.
3 Terminology 3.1 Sensitivity The sensitivity is represented in counts/g. In 2 g mode the sensitivity is 1024 counts/g. In 4 g mode the sensitivity is 512 counts/g and in 8 g mode the sensitivity is 256 counts/g. 3.2 Zero-g offset Zero-g offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y-axis whereas the Z-axis will measure 1 g.
4 System Modes (SYSMOD) OFF SYSMOD = 10 CTRL_REG1 Active bit = 0 VDD > 1.8 V Standby SYSMOD = 00 OFF VDD < 1.8 V Active Auto-sleep/wake Condition CTRL_REG1 Active bit = 1 CTRL_REG1 Active bit = 0 Wake SYSMOD = 01 Figure 6. MMA8452Q mode transition diagram Table 7. Mode of operation description I2C bus state Mode OFF Powered down VDD < 1.8 V VDDIO Can be > VDD Function description • The device is powered off. • All analog and digital blocks are shutdown. • I2C bus inhibited.
5 Functionality The MMA8452Q is a low-power, digital output 3-axis linear accelerometer with a I2C interface and embedded logic used to detect events and notify an external microprocessor over interrupt lines.
5.1 Device calibration The device interface is factory calibrated for sensitivity and zero-g offset for each axis. The trim values are stored in non-volatile memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the end application is not necessary. However, the MMA8452Q allows the user to adjust the zero-g offset for each axis after power-up, changing the default offset values.
5.5.2 Motion detection Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts.
Top View PU Pin 1 Side View Earth Gravity BACK LL LR Xout @ 0 g Yout @ –1 g Zout @ 0 g Xout @ 0 g Yout @ 0 g Zout @ –1 g FRONT PD Xout @ –1 g Yout @ 0 g Zout @ 0 g Xout @ 1 g Yout @ 0 g Zout @ 0 g Xout @ 0 g Yout @ 0 g Zout @ 1 g Xout @ 0 g Yout @ 1 g Zout @ 0 g Figure 7. Landscape/portrait orientation Portrait 90° Portrait 90° Landscape to portrait Trip angle = 60° Portrait to landscape Trip angle = 30° 0° Landscape 0° Landscape (A) (B) Figure 8.
5.9 Interrupt register configurations There are six configurable interrupts in the MMA8452Q: data-ready, motion/freefall, pulse, orientation, transient, and auto-sleep events. These six interrupt sources can be routed to one of two interrupt pins. The interrupt source must be enabled and configured. If the event flag is asserted because the event condition is detected, the corresponding interrupt pin, INT1 or INT2, will assert.
5.10.1 I2C operation The transaction on the bus is started through a start condition (start) signal. Start condition is defined as a high to low transition on the data line while the SCL line is held high. After start has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after start contains the slave address in the first seven bits, and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave.
I2C data sequence diagrams < Single-byte read > Master ST Device Address[6:0] W Register Address[7:0] AK Slave SR Device Address[6:0] R AK NAK SP AK Data[7:0] < Multiple-byte read > Master ST Device Address[6:0] W Register Address[7:0] AK Slave AK Master Data[7:0] R AK AK Data[7:0] Slave SR Device Address[6:0] AK AK NAK Data[7:0] SP Data[7:0] < Single-byte write > ST Master Device Address[6:0] W Register Address[7:0] AK Slave Data[7:0] AK SP AK < Multiple-byte
6 Register Descriptions Table 11. Register address map Name Type Register address Auto-increment address F_READ = 0 Default Hex value 00000000 0x00 F_READ = 1 Comment STATUS(1)(2) R 0x00 OUT_X_MSB(1)(2) R 0x01 0x02 0x03 Output — [7:0] are 8 MSBs of 12-bit sample. OUT_X_LSB(1)(2) R 0x02 0x03 0x00 Output — [7:4] are 4 LSBs of 12-bit sample. OUT_Y_MSB(1)(2) R 0x03 0x04 0x05 Output — [7:0] are 8 MSBs of 12-bit sample.
Table 11.
ZYXOW is set whenever a new acceleration data is produced before completing the retrieval of the previous set. This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten. ZYXOW is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the active channels are read. ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample.
0x0B: SYSMOD system mode register The system mode register indicates the current device operating mode. Applications using the auto-sleep/wake mechanism should use this register to synchronize the application with the device operating mode transitions. 0x0B: SYSMOD: system mode register (read only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 SYSMOD1 SYSMOD0 Table 13. SYSMOD description Field SYSMOD[1:0] Description System mode. Default value: 00.
Table 14. INT_SOURCE description (continued) Field Description SRC_FF_MT Freefall/motion interrupt status bit. Default value: 0. Logic ‘1’ indicates that the freefall/motion function interrupt is active. Logic ‘0’ indicates that no freefall or motion event was detected. This bit is asserted whenever EA bit in the FF_MT_SRC register is asserted and the FF_MT interrupt has been enabled. This bit is cleared by reading the FF_MT_SRC register. SRC_DRDY Data-ready interrupt bit status. Default value: 0.
0x0F: HP_FILTER_CUTOFF high-pass filter register This register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data. The output of this filter is indicated by the data registers (0x01-0x06) when bit 4 (HPF_OUT) of register 0x0E is set. The filter cutoff options change based on the data rate selected as shown in Table 18. For details of implementation on the high-pass filter, refer to NXP application note AN4071.
6.2 Portrait/landscape embedded function registers For more details on the meaning of the different user-configurable settings and for example code refer to NXP application note AN4068. 0x10: PL_STATUS portrait/landscape status register This status register can be read to get updated information on any change in orientation by reading bit 7, or on the specifics of the orientation by reading the other bits.
0x12: Portrait/landscape debounce counter This register sets the debounce count for the orientation state transition. The minimum debounce latency is determined by the data rate set by the product of the selected system ODR and PL_COUNT registers. Any transition from wake to sleep or vice versa resets the internal landscape/portrait debounce counter. Note: The debounce counter weighting (time step) changes based on the ODR and the oversampling mode.
Table 24. PL_THS_REG description Field Description Portrait/landscape fixed threshold angle = 1_0000 (45°). PL_THS[7:3] This is a fixed angle added to the threshold angle for a smoother transition from portrait to landscape and landscape to portrait. This angle is fixed at ±14°, which is 100. HYS[2:0] Table 25. Trip angles with hysteresis for 45° angle 6.
0x15: FF_MT_CFG freefall/motion configuration register This is the freefall/motion configuration register for setting up the conditions of the freefall or motion function. 0x15: FF_MT_CFG register (read/write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ELE OAE ZEFE YEFE XEFE 0 0 0 Table 26. FF_MT_CFG description Field Description ELE Event latch enable: Event flags are latched into FF_MT_SRC register. Reading of the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.
Table 27. Freefall/motion source description Field EA Description Event active flag. Default value: 0. 0: No event flag has been asserted; 1: One or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. ZHE Z-motion flag. Default value: 0. 0: No Z-motion event detected, 1: Z motion has been detected This bit reads always zero if the ZEFE control bit is set to zero ZHP Z-motion polarity flag. Default value: 0.
0x18: FF_MT_COUNT debounce register This register sets the number of debounce sample counts for the event trigger. 0x18: FF_MT_COUNT register (read/write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 Table 29. FF_MT_COUNT description Field Description Count value. Default value: 0000_0000 D[7:0] This register sets the minimum number of debounce sample counts of continuously matching the detection condition user selected for the freefall, motion event.
High-g Event on all 3-axis (Motion Detect) Count Threshold (a) FF Counter Value FFEA High-g Event on all 3-axis (Motion Detect) DBCNTM = 1 Count Threshold Debounce Counter Value (b) EA High-g Event on all 3-axis (Motion Detect) DBCNTM = 0 Count Threshold Debounce Counter Value (c) EA Figure 13.
6.4 Transient (HPF) acceleration detection For more information on the uses of the transient function please review NXP application note AN4071. This function is similar to the motion detection except that high-pass filtered data is compared. There is an option to disable the high-pass filter through the function. In this case the behavior is the same as the motion detection. This allows for the device to have two motion detection functions.
Table 32. TRANSIENT_SRC description (continued) Field XTRANSE X_Trans_Pol Description X-transient event. Default value: 0. 0: No interrupt, 1: X-transient acceleration greater than the value of TRANSIENT_THS event has occurred Polarity of X-transient event that triggered interrupt. Default value: 0. 0: X event was positive g, 1: X event was negative g When the EA bit gets set while ELE = 1, all other status bits get frozen at their current state.
Table 35. TRANSIENT_COUNT relationship with the ODR (continued) Max time range (s) Time step (ms) ODR (Hz) Normal LPLN HighRes LP Normal LPLN HighRes LP 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160 6.5 Single, double and directional pulse-detection registers For more details of how to configure the pulse detection and sample code, please refer to NXP application note AN4072.
Table 37. PULSE_SRC description Field Description EA Event active flag. Default value: 0. (0: No interrupt has been generated; 1: One or more interrupt events have been generated) AxZ Z-axis event. Default value: 0. (0: No interrupt; 1: Z-axis event has occurred) AxY Y-axis event. Default value: 0. (0: No interrupt; 1: Y-axis event has occurred) AxX X-axis event. Default value: 0. (0: No interrupt; 1: X-axis event has occurred) DPE Double pulse on first event. Default value: 0.
The threshold values range from 1 to 127 with steps of 0.063 g/LSB at a fixed 8 g acceleration range, thus the minimum resolution is always fixed at 0.063 g/LSB. If the low-noise bit in register 0x2A is set then the maximum threshold will be 4 g. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure. The threshold value is expressed over 7-bits as an unsigned number.
0x27: PULSE_LTCY pulse latency timer register 0x27: PULSE_LTCY register (read/write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0 Table 44. PULSE_LTCY description Field LTCY[7:0] Description Latency time limit. Default value: 0000_0000 The bits LTCY7 through LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored.
0x28: PULSE_WIND register (read/write) 0x28: PULSE_WIND second pulse time window register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0 Table 47. PULSE_WIND description Field WIND[7:0] Description Second pulse time window. Default value: 0000_0000.
6.6 Auto-wake/sleep detection The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value specified in the DR[2:0] register to ASLP_RATE register value, provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the return to sleep event.
6.7 Control registers Note: Except for standby mode selection, the device must be in standby mode to change any of the fields within CTRL_REG1 (0X2A). 0x2A: CTRL_REG1 system control 1 register 0x2A: CTRL_REG1 register (read/write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE Table 53. CTRL_REG1 description Field Description ASLP_RATE[1:0] Configures the auto-wake sample frequency when the device is in sleep mode.
ACTIVE bit selects between standby mode and active mode. The default value is 0 for standby mode. Table 56. Full-scale selection Active Mode 0 Standby 1 Active LNOISE bit selects between normal full dynamic range mode and a high sensitivity, low noise mode. In low noise mode, the maximum signal that can be measured is ±4 g. Note: Any thresholds set above 4 g will not be reached. F_READ bit selects between normal and fast-read mode.
Table 59. MODS oversampling modes current consumption and averaging values at each ODR Mode Normal (00) Low Noise Low Power (01) High Resolution (10) Low Power (11) ODR Current μA OS Ratio Current μA OS Ratio Current μA OS Ratio Current μA OS Ratio 1.56 Hz 24 128 8 32 165 1024 6 16 6.25 Hz 24 32 8 8 165 256 6 4 12.
Table 61. Interrupt enable register description (continued) Field Description INT_EN_LNDPRT Interrupt enable. Default value: 0. 0: Orientation (landscape/portrait) interrupt disabled. 1: Orientation (landscape/portrait) interrupt enabled. INT_EN_PULSE Interrupt enable. Default value: 0. 0: Pulse detection interrupt disabled; 1: Pulse detection interrupt enabled INT_EN_FF_MT Interrupt enable. Default value: 0.
Table 63. OFF_X description Field Description X-axis offset value. Default value: 0000_0000. D[7:0] 0x30: OFF_Y offset correction Y register 0x30: OFF_Y register (read/write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 Table 64. OFF_Y description Field Description Y-axis offset value. Default value: 0000_0000.
Table 66.
Table 67. Accelerometer output data (continued) 0000 0001 +0.0156 g +0.0313 g +0.0625 g 0000 0000 0.000 g 0.0000 g 0.0000 g 1111 1111 –0.0156 g –0.0313 g –0.0625 g … … … … 1000 0001 –1.9844 g –3.9688 g –7.9375 g 1000 0000 –2.0000 g –4.0000 g –8.
7 Printed Circuit Board Layout and Device Mounting Printed Circuit Board (PCB) layout and device mounting are critical portions of the total design. The footprint for the surface mount packages must be the correct size as a base for a proper solder connection between the PCB and the package. This, along with the recommended soldering materials and techniques, will optimize assembly and minimize the stress on the package after board mounting. 7.
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8 Package Information The MMA8452Q device is housed in a 16-lead QFN package, case number 98ASA00063D. 8.
8.2 Package description 98ASA00063D, 16-pin QFN, 3 mm x 3 mm x 1.
98ASA00063D, 16-pin QFN, 3 mm x 3 mm x 1.
98ASA00063D, 16-pin QFN, 3 mm x 3 mm x 1.
9 Revision History Table 68. Revision history Revision number Revision date Description of changes 10 04/2016 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Corrected Figure 6 title was MMA8451Q Mode Transition to MMA8452Q mode transition. • Table 8: Updated header to include Q suffix on device numbers. • Section 8.1: Deleted part marking information.
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