Datasheet

Sensors
18 NXP Semiconductors
MMA8452Q
I
2
C data sequence diagrams
Figure 11. I
2
C data sequence diagrams
< Single-byte read >
Master
ST Device Address[6:0] W Register Address[7:0] SR Device Address[6:0] R NAK SP
Slave
AK AK AK Data[7:0]
< Multiple-byte read >
Master
ST Device Address[6:0] W Register Address[7:0] SR Device Address[6:0] R AK
Slave
AK AK AK Data[7:0]
Master
AK AK NAK SP
Slave
Data[7:0] Data[7:0] Data[7:0]
< Single-byte write >
Master
ST Device Address[6:0] W Register Address[7:0] Data[7:0] SP
Slave
AK AK AK
< Multiple-byte write >
Master
ST Device Address[6:0] W Register Address[7:0] Data[7:0] Data[7:0] SP
Slave
AK AK AK AK
Legend
ST: Start condition SP: Stop condition NAK: No acknowledge W: Write = 0
SR: Repeated start condition AK: Acknowledge R: Read = 1