Datasheet

Sensors

34 NXP Semiconductors

MMA8452Q

6.5 Single, double and directional pulse-detection registers

For more details of how to configure the pulse detection and sample code, please refer to NXP application note AN4072. The

pulse-detection registers are referred to as pulse.

0x21: PULSE_CFG pulse configuration register

This register configures the event flag for the pulse detection for enabling/disabling the detection of a single and double pulse on

each of the axes.

0x22: PULSE_SRC pulse source register

This register indicates a double or single pulse event has occurred and also which direction. The corresponding axis and event

must be enabled in register 0x21 for the event to be seen in the source register.

12.5 5.1 20.4 0.638 20.4 20 80 2.5 80

6.25 5.1 20.4 0.638 40.8 20 80 2.5 160

1.56 5.1 20.4 0.638 40.8 20 80 2.5 160

0x21: PULSE_CFG Register (read/write)

Bit

DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE

Table 36.

PULSE_CFG description

Field Description

DPA

Double-pulse abort. Default value: 0.

0: Double-pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY register.

1: Setting the DPA bit momentarily suspends the double pulse detection if the start of a pulse is detected during the time period

specified by the PULSE_LTCY register and the pulse ends before the end of the time period specified by the PULSE_LTCY register.

ELE

Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag.

Default value: 0.

0: Event flag latch disabled; 1: Event flag latch enabled

ZDPEFE

Event flag enable on double pulse event on Z-axis. Default value: 0.