Datasheet

Sensors
NXP Semiconductors 37
MMA8452Q
0x27: PULSE_LTCY pulse latency timer register
The bits LTCY7 through LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses
are ignored. Note: This timer must be set for single pulse and for double pulse.
The minimum time step for the pulse latency is defined in Table 45 and Table 46. The maximum time is the time step at the ODR
and oversampling mode multiplied by 255. The timing also changes when the pulse LPF is enabled or disabled.
0x27: PULSE_LTCY register (read/write)
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0
Table 44. PULSE_LTCY description
Field Description
LTCY[7:0]
Latency time limit. Default value: 0000_0000
Table 45. Time step for pulse latency @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 1
ODR (Hz)
Max time range (s) Time step (ms)
Normal LPLN HighRes LP Normal LPLN HighRes LP
800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5
4001.2761.2761.2761.2765555
200 2.56 2.56 1.276 2.56 10 10 5 10
100 5.1 5.1 1.276 5.1 20 20 5 20
50 10.2 10.2 1.276 10.2 40 40 5 40
12.5 10.2 40.8 1.276 40.8 40 160 5 160
6.25 10.2 40.8 1.276 81.6 40 160 5 320
1.56 10.2 40.8 1.276 81.6 40 160 5 320
Table 46. Time step for pulse latency @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 0
ODR (Hz)
Max time range (s) Time step (ms)
Normal LPLN HighRes LP Normal LPLN HighRes LP
800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25
400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5
200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5
100 1.276 1.276 0.318 2.56 5 5 1.25 10
50 2.56 2.56 0.318 5.1 10 10 1.25 20
12.5 2.56 10.2 0.318 20.4 10 40 1.25 80
6.25 2.56 10.2 0.318 20.4 10 40 1.25 80
1.56 2.56 10.2 0.318 20.4 10 40 1.25 80