Datasheet

Sensors
40 NXP Semiconductors
MMA8452Q
6.7 Control registers
Note: Except for standby mode selection, the device must be in standby mode to change any of the fields within CTRL_REG1
(0X2A).
0x2A: CTRL_REG1 system control 1 register
It is important to note that when the device is auto-sleep mode, the system ODR and the data rate for all the system functional
blocks are overridden by the data rate set by the ASLP_RATE field.
DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 800 Hz.
0x2A: CTRL_REG1 register (read/write)
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE
Table 53. CTRL_REG1 description
Field Description
ASLP_RATE[1:0]
Configures the auto-wake sample frequency when the device is in sleep mode. Default value: 00.
See Table 54 for more information.
DR[2:0]
Data rate selection. Default value: 000.
See Table 55 for more information.
LNOISE
Reduced noise reduced maximum range mode. Default value: 0.
(0: Normal mode; 1: Reduced noise mode)
F_READ
Fast-read mode: Data format limited to single byte. Default value: 0.
(0: Normal mode 1: Fast-read mode)
ACTIVE
Full-scale selection. Default value: 00.
(0: Standby mode; 1: Active mode)
Table 54. Sleep mode rate description
ASLP_RATE1 ASLP_RATE0 Frequency (Hz)
00 50
0 1 12.5
1 0 6.25
1 1 1.56
Table 55. System output data rate selection
DR2 DR1 DR0 ODR Period
0 0 0 800 Hz 1.25 ms
0 0 1 400 Hz 2.5 ms
0 1 0 200 Hz 5 ms
0 1 1 100 Hz 10 ms
1 0 0 50 Hz 20 ms
1 0 1 12.5 Hz 80 ms
1 1 0 6.25 Hz 160 ms
1 1 1 1.56 Hz 640 ms