Datasheet
Sensors
42 NXP Semiconductors
MMA8452Q
0x2C: CTRL_REG3 interrupt control register
IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ (default value) any interrupt event will signaled with a
logical 0.
PP_OD bit configures the interrupt pin to push-pull or in open drain mode. The default value is 0 which corresponds to push-Pull
mode. The open drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.
0x2D: CTRL_REG4 register (read/write)
Table 59. MODS oversampling modes current consumption and averaging values at each ODR
Mode Normal (00) Low Noise Low Power (01) High Resolution (10) Low Power (11)
ODR Current
μA OS Ratio Current μA OS Ratio Current μA OS Ratio Current μAOS Ratio
1.56 Hz 24 128 8 32 165 1024 6 16
6.25 Hz 24 32 8 8 165 256 6 4
12.5 Hz 24 16 8 4 165 128 6 2
50 Hz 24 4 24 4 165 32 14 2
100 Hz 44 4 44 4 165 16 24 2
200 Hz 85 4 85 4 165 8 44 2
400 Hz 165 4 165 4 165 4 85 2
800 Hz 165 2 165 2 165 2 165 2
0x2C: CTRL_REG3 register (read/write)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
0 WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT 0 IPOL PP_OD
Table 60. CTRL_REG3 description
Field Description
WAKE_TRANS
0: Transient function is bypassed in sleep mode. Default value: 0.
1: Transient function interrupt can wake up system
WAKE_LNDPRT
0: Orientation function is bypassed in sleep mode. Default value: 0.
1: Orientation function interrupt can wake up system
WAKE_PULSE
0: Pulse function is bypassed in sleep mode. Default value: 0.
1: Pulse function interrupt can wake up system
WAKE_FF_MT
0: Freefall/motion function is bypassed in sleep mode. Default value: 0.
1: Freefall/motion function interrupt can wake up
IPOL
Interrupt polarity active high, or active low. Default value: 0.
0: Active low; 1: Active high
PP_OD
Push-pull/open drain selection on interrupt pad. Default value: 0.
0: Push-pull; 1: Open drain
0x2D: CTRL_REG4 register (read/write)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
INT_EN_ASLP 0 INT_EN_TRANS INT_EN_LNDPRT INT_EN_PULSE INT_EN_FF_MT 0 INT_EN_DRDY
Table 61.
Interrupt enable register description
Field Description
INT_EN_ASLP
Interrupt enable. Default value: 0.
0: Auto-sleep/wake interrupt disabled; 1: Auto-sleep/wake interrupt enabled.
INT_EN_TRANS
Interrupt enable. Default value: 0.
0: Transient interrupt disabled; 1: Transient interrupt enabled.