Atmel 8-bit Microcontroller with 4/8/16/32KBytes InSystem Programmable Flash ATmega48A; ATmega48PA; ATmega88A; ATmega88PA; ATmega168A; ATmega168PA; ATmega328; ATmega328P Features • High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family • Advanced RISC Architecture • • • • • – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20MHz – On-chip 2-cycle Multiplier High Endurance Non-v
• Operating Voltage: – 1.8 - 5.5V • Temperature Range: – -40C to 85C • Speed Grade: – 0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V • Power Consumption at 1MHz, 1.8V, 25C – Active Mode: 0.2mA – Power-down Mode: 0.1µA – Power-save Mode: 0.75µA (Including 32kHz RTC) 1.
Table 1-1. 32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA 1 2 3 4 5 6 A PD2 PD1 PC6 PC4 PC2 PC1 B PD3 PD4 PD0 PC5 PC3 PC0 C GND GND ADC7 GND D VDD VDD AREF ADC6 E PB6 PD6 PB0 PB2 AVDD PB5 F PB7 PD5 PD7 PB1 PB3 PB4 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
2. Overview The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram VCC Block Diagram GND Figure 2-1.
The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a
is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5.
7. AVR CPU Core Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
7.3.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
• One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr.
7.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 7.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
8. AVR Memories 8.1 Overview This section describes the different memories in the ATmega48A/PA/88A/PA/168A/PA/328/P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
Figure 8-1. Program Memory Map ATmega 48A/48PA Program Memory 0x0000 Application Flash Section 0x7FF Figure 8-2.
8.3 SRAM Data Memory Figure 8-3 shows how the ATmega48A/PA/88A/PA/168A/PA/328/P SRAM Memory is organized. The ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 8-4. Figure 8-4. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM memory.
8.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
8.6 8.6.
Table 8-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4ms Erase and Write in one operation (Atomic Operation) 0 1 1.8ms Erase Only 1 0 1.8ms Write Only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 38. The clock systems are detailed below. Figure 9-1.
9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a BrownOut Detection circuit is not recommended. The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable.
Notes: 1. This is the recommended CKSEL settings for the difference frequency ranges. 2. This option should not be used with crystals, only with ceramic resonators. 3. If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. The CKSEL0 Fuse together with the SUT1...
The operating mode is selected by the fuses CKSEL3...1 as shown in Table 9-5. Table 9-5. Full Swing Crystal Oscillator operating modes Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 (pF) 0.4 - 20 Notes: CKSEL3...1 12 - 22 011 1. If the cryatal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8.
9.5 Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega48A/PA/88A/PA/168A/PA/328/P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table for maximum ESR recommendations on 6.5pF, 9.0pF and 12.
Table 9-10. CKSEL3... 0 Start-up Time from Power-down and Power-save 0100(1) 1K CK 0101 32K CK Note: 9.6 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Recommended Usage Stable frequency at start-up 1. This option should only be used if frequency stability at start-up is not important for the application Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0MHz clock.
9.7 128kHz Internal Oscillator The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 9-13. Table 9-13. Note: 128kHz Internal Oscillator Operating Modes Nominal Frequency(1) CKSEL3...0 128kHz 0011 1. Note that the 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
Table 9-16. Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1...0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1ms 01 Slowly rising power 6 CK 14CK + 65ms 10 Power Conditions Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2.
9.12 9.12.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
Table 9-17.
10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See ”BOD Disable(1)” on page 39 for more details. 10.
10.2 BOD Disable(1) When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see Table 28-7 on page 287 and onwards, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 38. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note: If a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. ”External Interrupts” on page 71.
10.8 Extended Standby Mode When the SM2...0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 10.
10.10.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.
10.11 Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits [7:4]: Reserved These bits are unused in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always be read as zero.
10.11.2 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 6 – BODS: BOD Sleep(1) The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 10-1 on page 38. Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR.
• Bit 1 – PRUSART0: Power Reduction USART0 Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For ATmega168A/168PA/328/328P the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega 48A/48PA and ATmega88A/88PA, the instruction placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset handling routine.
Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 310.
Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 310) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 50 for details on operation of the Watchdog Timer. Figure 11-6. Watchdog System Reset During Operation CC CK 11.
11.8 Watchdog Timer 11.8.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Overview ATmega48A/PA/88A/PA/168A/PA/328/P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<
11.9 Register Description 11.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 7:4: Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 11-1. Watchdog Timer Configuration (1) WDTON WDE WDIE Mode Action on Time-out 1 0 0 Stopped None 1 0 1 Interrupt Mode Interrupt 1 1 0 System Reset Mode Reset 1 1 1 Interrupt and System Reset Mode Interrupt, then go to System Reset Mode 0 x x System Reset Mode Reset Note: 1.
Table 11-2. Watchdog Timer Prescale Select (Continued) WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
12. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega48A/PA/88A/PA/168A/PA/328/P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 13.
Table 12-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA (Continued) Vector No.
12.2 Interrupt Vectors in ATmega88A and ATmega88PA Table 12-2. Reset and Interrupt Vectors in ATmega88A and ATmega88PA Vector No.
Table 12-3. Reset and Interrupt Vectors Placement in ATmega88A and ATmega88PA(1) BOOTRST IVSEL 1 Note: Reset Address Interrupt Vectors Start Address 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001 1. The Boot Reset Address is shown in Table 27-7 on page 280. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is: Address Labels Code Comments 0x000 RESET: ldi 0x001 out SPH,r16 r16,high(RAMEND); Main program start 0x002 ldi r16,low(RAMEND) 0x003 0x004 out sei SPL,r16 0x005 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx
12.3 0xC1D 0xC1E out sei SPL,r16 0xC1F ; Enable interrupts xxx Interrupt Vectors in ATmega168A and ATmega168PA Table 12-4. VectorNo.
ular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-5. Reset and Interrupt Vectors Placement in ATmega168A and ATmega168PA(1) BOOTRST IVSEL 1 Note: Reset Address Interrupt Vectors Start Address 0 0x000 0x002 1 1 0x000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x002 0 1 Boot Reset Address Boot Reset Address + 0x0002 1.
0x0038 ... ... ... xxx ...
12.4 0x1C33 RESET: ldi r16,high(RAMEND); Main program start 0x1C34 out SPH,r16 0x1C35 ldi r16,low(RAMEND) 0x1C36 0x1C37 out sei SPL,r16 0x1C38 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Interrupt Vectors in ATmega328 and ATmega328P Table 12-6. Reset and Interrupt Vectors in ATmega328 and ATmega328P VectorNo.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. Table 12-7 on page 66 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei 0x0038 ... ; Enable interrupts ... ... xxx ...
0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x3C33 RESET: ldi r16,high(RAMEND); Main program start 0x3C34 out SPH,r16 0x3C35 ldi r16,low(RAMEND) 0x3C36 0x3C37 out sei SPL,r16 0x3C38 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET] 8271E–AVR–07/2012 68
12.5 Register Description 12.5.1 Moving Interrupts Between Application and Boot Space, ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P The MCU Control Register controls the placement of the Interrupt Vector table. MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1.
Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
13. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles.
13.2 Register Description 13.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 (0x69) – – – – ISC11 ISC10 ISC01 ISC00 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 7:4 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
13.2.2 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x1D (0x3D) – – – – – – INT1 INT0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bit 7:2 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
• Bit 7:3 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 13.2.
14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET SLEEP RRx SYNCHRONIZER D Q L Q D WRx WPx RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 14.2.
14.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not notice the difference between a strong high driver and a pull-up.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 14-4.
Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 on page 81 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Table 14-3.
inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0. • SCK/PCINT5 – Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB0 and DDB0 settings. It will also be output during reset. PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source. Table 14-4 and Table 14-5 on page 86 relate the alternate functions of Port B to the overriding signals shown in Figure 14-5 on page 81.
Table 14-5. 14.3.2 Overriding Signals for Alternate Functions in PB3...
The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0. PCINT14: Pin Change Interrupt source 14.
• ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.
Table 14-8. 14.3.3 Overriding Signals for Alternate Functions in PC3...
• AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt source. • AIN0/OC0A/PCINT22 – Port D, Bit 6 AIN0, Analog Comparator Positive Input.
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. Table 14-10 and Table 14-11 relate the alternate functions of Port D to the overriding signals shown in Figure 14-5 on page 81. Table 14-10. Overriding Signals for Alternate Functions PD7...
14.4 14.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Notes: MCUCR 1.
14.4.8 PORTD – The Port D Data Register Bit 14.4.9 7 6 5 4 3 2 1 0 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRD – The Port D Data Direction Register Bit 14.4.
15. 8-bit Timer/Counter0 with PWM Features • • • • • • • 15.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
15.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 15-1 are also used extensively throughout the document.
Figure 15-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count TCNTn clear Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value.
Figure 15-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 15.6 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 15-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting.
15.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 N 1 + OCRnx The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
the WGM02 bit is set. This option is not available for the OC0B pin (see Table 15-6 on page 106). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
Figure 15-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
15.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 15-8.
Figure 15-11.
15.9 15.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
Table 15-7. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP.
15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Table 15-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 15-8, ”Waveform Generation Mode Bit Description” on page 107.
16. 16-bit Timer/Counter1 with PWM 16.1 Features • • • • • • • • • • • 16.2 True 16-bit Design (i.e.
Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 16.2.1 TCCRnB 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”Analog Comparator” on page 239) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.
Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. See ”About Code Examples” on page 7. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O.
Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1.
Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1.
16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number.
Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 17-1 on page 139). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
Figure 16-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 16-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf.
16.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 16.7.
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions.
counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 16-6.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
rements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 16-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
Figure 16-12. Timer/Counter Timing Diagram, no Prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13.
16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 16-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
Waveform Generation Mode Bit Description(1) (Continued) Table 16-4. Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) 13 1 1 0 14 1 1 15 1 1 Note: 16.11.2 Timer/Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 1 (Reserved) – – – 1 0 Fast PWM ICR1 BOTTOM TOP 1 1 Fast PWM OCR1A BOTTOM TOP 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions.
Table 16-5. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A Bit 16.11.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 57) is executed when the ICF1 Flag, located in TIFR1, is set. • Bit 4, 3 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
17. Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 94 and ”16-bit Timer/Counter1 with PWM” on page 112 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 17-2.
17.4 17.4.1 Register Description GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • • • • • • • 18.2 Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value.
count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2).
Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence.
Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 18.6 Compare Match Output Unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting.
18.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 N 1 + OCRnx The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table 18-3 on page 155). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
Figure 18-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
18.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 18-11.
18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c. Write new values to TCNT2, OCR2x, and TCCR2x. d.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge.
18.11 Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
Table 18-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR2A equals TOP and COM2A1 is set.
Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 18-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: Description 1.
18.11.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
Table 18-9. Clock Select Bit Description CS22 CS21 CS20 Description 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 18.11.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 5 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. • Bit 4 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 199. The PRSPI bit in ”Minimizing Power Consumption” on page 41 must be written to zero to enable SPI module. Figure 19-1.
when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1 on page 164. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 81. Table 19-1.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
19.5 19.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
Table 19-5. 19.5.
19.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
20. USART0 20.1 Features • • • • • • • • • • • • 20.
Figure 20-1. USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR 20.3 TxDn Receiver UCSRnA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnB RxDn UCSRnC 1. Refer to Figure 1-1 on page 2 and Table 14-9 on page 89 for USART0 pin placement.
Figure 20-2 shows a block diagram of the clock generation logic. Figure 20-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector 0 UCPOLn txclk UMSELn 1 xcko DDR_XCKn 1 1 0 rxclk Signal description: 20.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Table 20-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of metastability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK ----------4 Note that fosc depends on the stability of the system clock source.
Figure 20-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
20.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
Assembly Code Example(1)(2) USART_Transmit: ; Wait for empty transmit buffer in r16, UCSRnA sbrs r16, UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received in r16, UCSRnA sbrs r16, UDREn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
Assembly Code Example(1) USART_Receive: ; Wait for data to be received in r16, UCSRnA sbrs r16, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
20.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 20.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.
Figure 20-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 20-7. For Double Speed mode the first low level must be delayed to (B).
Table 20-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 94.12 105.66 +5.66/-5.88 ± 2.5 6 94.92 104.92 +4.92/-5.08 ± 2.0 7 95.52 104,35 +4.35/-4.48 ± 1.5 8 96.00 103.90 +3.90/-4.00 ± 1.5 9 96.39 103.53 +3.53/-3.61 ± 1.5 10 96.70 103.23 +3.23/-3.30 ± 1.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5.
Table 20-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000MHz fosc = 1.8432MHz Baud Rate (bps) UBRRn 2400 25 0.2% 51 0.2% 47 4800 12 0.2% 25 0.2% 9600 6 -7.0% 12 14.4k 3 8.5% 19.2k 2 28.8k U2Xn = 0 U2Xn = 1 UBRRn Error 0.0% 95 0.0% 51 0.2% 103 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.
Table 20-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz Baud Rate (bps) U2Xn = 0 fosc = 4.0000MHz U2Xn = 1 U2Xn = 0 fosc = 7.3728MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.
Table 20-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.
Table 20-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.
20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDRn Register location.
• Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled.
• Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 20-9.
Table 20-12. UCPOLn Bit Settings Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge UCPOLn 20.11.
21. USART in SPI Mode 21.1 Features • • • • • • • • 21.
21.4 fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 21-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize.
21.5.1 USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the Receiver. Only the transmitter can operate independently.
Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
21.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer in r16, UCSRnA sbrs r16, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: in r16, UCSRnA sbrs r16, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
21.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit. • The UCPHAn bit functionality is identical to the SPI CPHA bit. • The UDORDn bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
21.8 Register Description The following section describes the registers used for SPI operation using the USART. 21.8.1 21.8.2 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See ”UDRn – USART I/O Data Register n” on page 194.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port operation for the RxDn pin when enabled.
• Bit 1 – UCPHAn: Clock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details. • Bit 0 – UCPOLn: Clock Polarity The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details. 21.8.
22. 2-wire Serial Interface 22.1 Features • • • • • • • • • • • 22.
22.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 22-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. The PRTWI bit in ”Minimizing Power Consumption” on page 41 must be written to zero to enable the 2-wire Serial Interface.
22.3.2 START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition.
Figure 22-4. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SDA SCL 1 2 START 22.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle.
Figure 22-6. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB 7 8 9 1 Data LSB ACK 8 9 SDA SCL 1 START 22.4 2 SLA+R/W 2 7 Data Byte STOP Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.
Figure 22-7. SCL Synchronization Between Multiple Masters TA low TA high SCL from Master A SCL from Master B SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration.
• A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 22.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 22-9.
times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency = ----------------------------------------------------------------------------------------16 + 2(TWBR) PrescalerValue • TWBR = Value of the TWI Bit Rate Register. • PrescalerValue = Value of the prescaler, see Table 22-7 on page 236. Note: 22.5.
• After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. 22.6 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent.
Table 2. Assembly Code Example ldi r16, (1<
22.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free.
Table 22-2.
Figure 22-12. Formats and States in the Master Transmitter Mode MT Successfull transmission to a slave receiver S SLA $08 W A DATA $18 A P $28 Next transfer started with a repeated start condition RS SLA W $10 Not acknowledge received after the slave address A R P $20 MR Not acknowledge received after a data byte A P $30 Arbitration lost in slave address or data byte A or A Other master continues $38 Arbitration lost and addressed as slave From slave to master 22.7.
Figure 22-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
Table 22-3.
Figure 22-14. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA R A DATA A $40 $08 DATA $50 A P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A W P $48 MT Arbitration lost in slave address or data byte A or A Other master continues A $38 Arbitration lost and addressed as slave A $68 From master to slave 22.7.
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 22-4.
Figure 22-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 22-5.
Figure 22-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as slave DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave A From slave to master 22.7.
in a multi master system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 22-19.
Figure 22-21.
22.9 22.9.1 Register Description TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB8) TWBR • Bits 7...0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
• Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
22.9.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 (0xBB) TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
Figure 22-22. TWI Address Match Logic, Block Diagram TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 • Bit 0 – Reserved This bit is an unused bit in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
23. Analog Comparator 23.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 23-1. 23.3 23.3.1 Analog Comparator Multiplexed Input (Continued) ACME ADEN MUX2...
• Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator.
24. Analog-to-Digital Converter 24.1 Features • • • • • • • • • • • • • • 24.2 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260µs Conversion Time Up to 76.9kSPS (Up to 15kSPS at Maximum Resolution) 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only) Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
Figure 24-1. Analog to Digital Converter Block Schematic Operation, ADC CONVERSION COMPLETE IRQ ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADFR ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 1.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 24.3 Starting a Conversion A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 41 by writing a logical zero to it and writing a logical one to the ADC Start Conversion bit, ADSC.
Prescaling and Conversion Timing Figure 24-3. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 CK CK/2 24.4 ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
Figure 24-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update Figure 24-5.
Figure 24-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 24-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 24.
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC.
mended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 24-8. Analog Input Circuitry IIH ADCn 1..
Analog Ground Plane PC2 (ADC2) PC3 (ADC3) PC4 (ADC4/SDA) PC5 (ADC5/SCL) VCC GND Figure 24-9. ADC Power Connections PC1 (ADC1) PC0 (ADC0) ADC7 10µH GND AREF 100nF ADC6 AVCC PB5 24.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
• Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 24-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 24-12.
Figure 24-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB. • Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
temperature measurement can be calibrated in the application software. The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each chip, as a part of the production test. The software calibration can be done utilizing the formula: T = { [(ADCH << 8) | ADCL] - TOS} / k where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sensor offset value determined and stored into EEPROM as a part of the production test.
24.9 24.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS[1:0]: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 24-3.
Table 24-4. MUX3...0 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 ADC8(1) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1V (VBG) 1111 0V (GND) Note: 24.9.2 Input Channel Selections 1. For Temperature Sensor.
• Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• Bit 5:0 – ADC5D...ADC0D: ADC5...0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC5...0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
25. debugWIRE On-chip Debug System 25.1 Features • • • • • • • • • • 25.
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 25.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
26. Self-Programming the Flash, ATmega 48A/48PA 26.1 Overview In ATmega 48A/48PA there is no Read-While-Write support, and no separate Boot Loader Section. The SPM instruction can be executed from the entire Flash. The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory.
26.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 26.2 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
26.2.2 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
26.2.3 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
26.2.5 Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in ATmega 48A/48PA. Nevertheless, it is recommended to check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
ld cpse rjmp sbiw brne r1, Y+ r0, r1 Error loophi:looplo, 1 Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
26.3 Register Description 26.3.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.
• Bit 0 – SPMEN: Store Program Memory This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
27. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support applies to ATmega88A/88PA/168A/168PA/328/328P 27.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 27.2 1.
(RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 27-8 on page 280 and Figure 27-2 on page 272. The main difference between the two sections is: • When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.
Figure 27-1. Read-While-Write vs.
Figure 27-2.
Table 27-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
27.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 28-11 on page 290), the Program Counter can be treated as having two different sections.
27.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ware. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in ”Interrupts” on page 57. 27.8.5 Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed.
an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 28-5 on page 287 for a detailed description and mapping of the Fuse Low byte. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer.
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
27.8.14 ATmega88A and ATmega88PA Boot Loader Parameters In Table 27-7 through Table 27-9, the parameters used in the description of the self programming are given. Table 27-7.
27.8.15 ATmega168A and ATmega168PA Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-10.
27.8.16 ATmega328 and ATmega328P Boot Loader Parameters In Table 27-13 through Table 27-15, the parameters used in the description of the self programming are given. Table 27-13.
27.9 Register Description 27.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
• Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
28. Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega 48A/48PA provides two Lock bits and the ATmega88A/88PA/168A/168PA/328/328Pprovides six Lock bits. These can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command.
Table 28-3. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
Table 28-5. Extended Fuse Byte for ATmega88A/88PA/168A/168PA Extended Fuse Byte Bit No Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 – 3 – 1 2 Select Boot Size (see Table 27-7 on page 280 and Table 27-10 on page 281 for details) 0 (programmed)(1) BOOTSZ0 1 Select Boot Size (see Table 27-7 on page 280 and Table 27-10 on page 281 for details) 0 (programmed)(1) BOOTRST 0 Select Reset Vector 1 (unprogrammed) BOOTSZ1 Note: 1.
Table 28-7. Fuse High Byte for ATmega48A/48PA/88A/88PA/168A/168PA (Continued) High Fuse Byte (4) (4) (4) Bit No BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: 1. 2. 3. 4. Description Default Value 2 Brown-out Detector trigger level 1 (unprogrammed) 1 Brown-out Detector trigger level 1 (unprogrammed) 0 Brown-out Detector trigger level 1 (unprogrammed) See ”Alternate Functions of Port C” on page 86 for description of RSTDISBL Fuse. The SPIEN Fuse is not accessible in serial programming mode.
Table 28-9. Fuse Low Byte (Continued) Low Fuse Byte Bit No Description Default Value CKSEL2 2 Select Clock source 0 (programmed)(2) CKSEL1 1 Select Clock source 1 (unprogrammed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) Note: 1. The default value of SUT1...0 results in maximum start-up time for the default clock source. See Table 9-12 on page 32 for details. 2. The default setting of CKSEL3...0 results in internal RC Oscillator @ 8MHz. See Table 9-11 on page 32 for details. 3.
28.5 Page Size Table 28-11. No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD No.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 28-15. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 28-16. Figure 28-1. Parallel Programming +4.5 - 5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL VCC +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA PD7 +12 V RESET BS2 PC2 XTAL1 GND Note: VCC - 0.3V < AVCC < VCC + 0.
Table 28-14. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 28-15. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 28-16.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 1. Set Prog_enable pins listed in Table 28-14 on page 292 to “0000”, RESET pin to 0V and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET. 4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5.
4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”.
Figure 28-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 28-11 on page 290. Figure 28-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 28-4 for signal waveforms). Figure 28-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 28.7.
3. Give WR a negative pulse and wait for RDY/BSY to go high. 28.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 293 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”.
The Lock bits can only be cleared by executing Chip Erase. 28.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash” on page 293 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”.
28.7.15 Parallel Programming Characteristics For characteristics of the Parallel Programming, see ”Parallel Programming Characteristics” on page 316. 28.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
When reading data from the ATmega48A/PA/88A/PA/168A/PA/328/P, data is clocked on the falling edge of SCK. See Figure 28-9 for timing details. To program and verify the ATmega48A/PA/88A/PA/168A/PA/328/P in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 28-19 on page 301): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
28.8.3 Serial Programming Instruction set Table 28-19 on page 301 and Figure 28-8 on page 302 describes the Instruction set. Table 28-19.
After data is loaded to the page buffer, program the EEPROM page, see Figure 28-8 on page 302. Figure 28-8.
29. Electrical Characteristics 29.1 Absolute Maximum Ratings* *NOTICE: Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 29-1. Common DC characteristics TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter RPU I/O Pin Pull-up Resistor VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Typ. 20 <10 -50 Max. Units 50 k 40 mV 50 nA 750 500 ns 1.
29.2.2 ATmega48PA DC Characteristics Table 29-3. Symbol ATmega48PA Dc characteristics TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC (3) Power-save mode Power-down mode(3) Notes: Max. Units Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 1.2 2.5 mA Active 8MHz, VCC = 5V 4.0 9 mA Idle 1MHz, VCC = 2V 0.03 0.15 mA Idle 4MHz, VCC = 3V 0.21 0.7 mA Idle 8MHz, VCC = 5V 0.9 2.7 mA 32kHz TOSC enabled, VCC = 1.8V 0.
29.2.4 ATmega88PA DC Characteristics Table 29-5. Symbol ATmega88PA DC characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC (3) Power-save mode Power-down mode(3) Notes: Max. Units Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 1.2 2.5 mA Active 8MHz, VCC = 5V 4.1 9 mA Idle 1MHz, VCC = 2V 0.03 0.15 mA Idle 4MHz, VCC = 3V 0.18 0.7 mA Idle 8MHz, VCC = 5V 0.8 2.7 mA 32kHz TOSC enabled, VCC = 1.8V 0.
29.2.6 ATmega168PA DC Characteristics Table 29-7. Symbol ATmega168PA Dc characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC (3) Power-save mode Power-down mode(3) Notes: Max. Units Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 1.2 2.5 mA Active 8MHz, VCC = 5V 4.2 9 mA Idle 1MHz, VCC = 2V 0.03 0.15 mA Idle 4MHz, VCC = 3V 0.2 0.7 mA Idle 8MHz, VCC = 5V 0.9 2.7 32kHz TOSC enabled, VCC = 1.8V 0.
29.2.8 ATmega328P DC Characteristics Table 29-9. Symbol ATmega328P Dc characteristics - TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Typ.(2) Max. Units Active 1MHz, VCC = 2V 0.3 0.5 mA Active 4MHz, VCC = 3V 1.7 2.5 mA Active 8MHz, VCC = 5V 5.2 9 mA Idle 1MHz, VCC = 2V 0.04 0.15 mA Idle 4MHz, VCC = 3V 0.3 0.7 mA Idle 8MHz, VCC = 5V 1.2 2.7 mA 32kHz TOSC enabled, VCC = 1.8V 0.8 1.6 µA 32kHz TOSC enabled, VCC = 3V 0.9 2.
29.4 Clock Characteristics 29.4.1 Calibrated Internal RC Oscillator Accuracy Table 29-10. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0MHz 3V 25C ±10% User Calibration 7.3 - 8.1MHz 1.8V - 5.5V -40C - 85C ±1% 29.4.2 External Clock Drive Waveforms Figure 29-2. External Clock Drive Waveforms V IH1 V IL1 29.4.3 External Clock Drive Table 29-11. External Clock Drive VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.
29.5 System and Reset Characteristics Table 29-12. Reset, Brown-out and Internal Voltage Characteristics(1) Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) SRON Power-on Slope Rate VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin (2) Min. Typ Max Units 1.1 1.4 1.6 V 0.6 1.3 1.6 V 0.01 10 V/ms 0.2 VCC 0.9 VCC V 2.5 µs Brown-out Detector Hysteresis 50 mV tBOD Min.
29.6 SPI Timing Characteristics See Figure 29-3 and Figure 29-4 for details. Table 29-14. SPI Timing Parameters Description Mode 1 SCK period Master See Table 19-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 29-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
29.7 Two-wire Serial Interface Characteristics Table 29-15 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-5. Table 29-15. Two-wire Serial Bus Requirements Symbol Parameter VIL Min. Max Units Input Low-voltage -0.5 0.3 VCC V VIH Input High-voltage 0.7 VCC VCC + 0.
3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. Figure 29-5.
29.8 ADC Characteristics Table 29-16. ADC Characteristics Symbol Parameter Condition Min. Resolution VIN Units Bits VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1MHz 4.5 LSB VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1MHz Noise Reduction Mode 4.5 LSB Integral Non-Linearity (INL) VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.
29.9 Parallel Programming Characteristics Table 29-17. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min. VPP Programming Enable Voltage 11.
Figure 29-6. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 29-7.
30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
Active Supply Current Figure 30-1. ATmega48A: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.1.1 ATmega48A Typical Characteristics 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-2. ATmega48A: Active Supply Current vs. Frequency (1-20MHz 12 5.5 V 10 5.0 V 8 ICC (mA) 30.1 4.5 V 6 4.0 V 4 3.3 V 2 2.7 V 1.
Figure 30-3. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.14 85 °C -40 °C 25 °C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-4. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-5. ATmega48A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 30-6. ATmega48A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.16 5.5 V 0.14 ICC (mA) 30.1.2 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-7. ATmega48A: Idle Supply Current vs. Frequency (1-20MHz) 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-8. ATmega48A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.042 85 °C 0.035 25 °C ICC (mA) 0.028 -40 °C 0.021 0.014 0.007 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-9. ATmega48A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-10. ATmega48A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.1.3 ATmega48A: Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-1.
Power-down Supply Current Figure 30-11. ATmega48A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1.2 85 °C 1 ICC (uA) 0.8 0.6 0.4 -40 °C 25 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-12. ATmega48A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 -40 °C 85 °C 25 °C 6 ICC (uA) 30.1.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.1.5 Power-save Supply Current Figure 30-13. ATmega48A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2 85 °C ICC (uA) 1.6 25 °C 1.2 -40 °C 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-14. ATmega48A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled 0.16 6MHz_xtal 6MHz_res 0.14 0.12 4MHz_res 4MHz_xtal 0.1 ICC (mA) 30.1.6 0.08 2MHz_res 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.5 2 2.
Pin Pull-Up Figure 30-15. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 30-16. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 70 60 50 IOP (uA) 30.1.7 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
Figure 30-17. ATmega48A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 1 2 3 4 5 VOP (V) Figure 30-18. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)) 35 30 IRESET (uA) 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-19. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-20. ATmega48A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 20 25 °C -40 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Driver Strength Figure 30-21. ATmega48A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C 0.6 VOL (V) -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-22. ATmega48A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) VOL (V) 30.1.8 0.6 85 °C 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.
Figure 30-23. ATmega48A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-24. ATmega48A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 4.
Pin Threshold and Hysteresis Figure 30-25. ATmega48A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-26. ATmega48A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C 2 Threshold (V) 30.1.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-27. ATmega48A: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-28. ATmega48A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1)’ -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-29. )ATmega48A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-30. ATmega48A: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 25 °C -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-31. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.85 Rising Vcc 1.84 Threshold (V) 1.83 1.82 Falling Vcc 1.81 1.8 1.79 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-32. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.1.10 2.7 2.68 Falling Vcc 2.66 2.64 2.
Figure 30-33. ATmega48A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.36 Rising Vcc 4.34 Threshold (V) 4.32 4.3 4.28 Falling Vcc 4.26 4.24 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-34. ATmega48A: Bandgap Voltage vs. VCC 1.104 Bandgap Voltage (V) 1.102 85 °C 1.1 25 °C 1.098 1.096 -40 °C 1.094 1.092 1.09 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-35. ATmega48A: Watchdog Oscillator Frequency vs. Temperature 116 114 FRC (kHz) 112 110 2.7 V 3.3 V 4.0 V 5.5 V 108 106 104 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-36. ATmega48A: Watchdog Oscillator Frequency vs. VCC 118 116 FRC (kHz) 30.1.11 114 -40 °C 112 25 °C 110 108 85 °C 106 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-37. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 FRC (MHz) 8 25 °C 7.9 7.8 -40 °C 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-38. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.2 3.3 V 5.5 V 1.8 V 8.1 FRC (MHz) 8 7.9 7.8 7.7 7.
Figure 30-39. ATmega48A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 16 85 °C 25 °C -40 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-40. ATmega48A: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 250 ICC (uA) 30.1.12 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-41. ATmega48A: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-42. ATmega48A: AREF External Reference Current vs. VCC 160 85 °C 25 °C -40 °C 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-43. ATmega48A Brownout Detector Current vs. VCC 40 ICC (uA) 32 85 °C 25 °C -40 °C 24 16 8 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-44. ATmega48A: Programming Current vs. VCC 6 -40 °C 5 25 °C ICC (mA) 4 3 85 °C 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-45. ATmega48A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) ICC (mA) 0.14 0.12 5.5 V 0.1 5.0 V 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 0.02 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-46. ATmega48A: Reset Supply Current vs. Frequency (1 - 20MHz) 2.5 5.5 V 2 5.0 V 4.5 V ICC (mA) 30.1.13 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-47. ATmega48A: Minimum Reset Pulse width vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active Supply Current Figure 30-48. ATmega48PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.2.1 ATmega48PA Typical Characteristics 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-49. ATmega48PA: Active Supply Current vs. Frequency (1-20MHz) 12 5.5 V 10 5.0 V 8 ICC (mA) 30.2 4.5 V 6 4.0 V 4 3.3 V 2 2.7 V 1.
Figure 30-50. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.14 85 °C -40 °C 25 °C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-51. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-52. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 30-53. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.16 5.5 V 0.14 ICC (mA) 30.2.2 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-54. ATmega48PA: Idle Supply Current vs. Frequency (1-20MHz) 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-55. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.042 85 °C 0.035 25 °C ICC (mA) 0.028 -40 °C 0.021 0.014 0.007 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-56. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-57. ATmega48PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.2.3 ATmega48PA: Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-3.
Power-down Supply Current Figure 30-58. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1.2 85 °C 1 ICC (uA) 0.8 0.6 0.4 -40 °C 25 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-59. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 -40 °C 85 °C 25 °C 6 ICC (uA) 30.2.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.2.5 Power-save Supply Current Figure 30-60. ATmega48PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2 85 °C ICC (uA) 1.6 25 °C 1.2 -40 °C 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-61. ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.16 6MHz_xtal 6MHz_res 0.14 0.12 4MHz_res 4MHz_xtal 0.1 ICC (mA) 30.2.6 0.08 2MHz_res 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.5 2 2.
Pin Pull-Up Figure 30-62. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 30-63. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 70 60 50 IOP (uA) 30.2.7 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
Figure 30-64. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 1 2 3 4 5 VOP (V) Figure 30-65. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 35 30 IRESET (uA) 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-66. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-67. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) 120 100 IRESET (uA) 80 60 40 20 25 °C -40 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Driver Strength Figure 30-68. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C 0.6 VOL (V) -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-69. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) VOL (V) 30.2.8 0.6 85 °C 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.
Figure 30-70. ATmega48PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-71. ATmega48PA: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 4.
Pin Threshold and Hysteresis Figure 30-72. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-73. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C 2 Threshold (V) 30.2.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-74. ATmega48PA: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-75. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-76. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-77. ATmega48PA: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 25 °C -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-78. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.85 Rising Vcc 1.84 Threshold (V) 1.83 1.82 Falling Vcc 1.81 1.8 1.79 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-79. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.2.10 2.7 2.68 Falling Vcc 2.66 2.64 2.
Figure 30-80. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.36 Rising Vcc 4.34 Threshold (V) 4.32 4.3 4.28 Falling Vcc 4.26 4.24 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-81. ATmega48PA: Bandgap Voltage vs. VCC 1.104 Bandgap Voltage (V) 1.102 85 °C 1.1 25 °C 1.098 1.096 -40 °C 1.094 1.092 1.09 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-82. ATmega48PA: Watchdog Oscillator Frequency vs. Temperature 116 114 FRC (kHz) 112 110 2.7 V 3.3 V 4.0 V 5.5 V 108 106 104 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-83. ATmega48PA: Watchdog Oscillator Frequency vs. VCC 118 116 FRC (kHz) 30.2.11 114 -40 °C 112 25 °C 110 108 85 °C 106 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-84. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 FRC (MHz) 8 25 °C 7.9 7.8 -40 °C 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-85. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.2 3.3 V 5.5 V 1.8 V 8.1 FRC (MHz) 8 7.9 7.8 7.7 7.
Figure 30-86. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 16 85 °C 25 °C -40 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-87. ATmega48PA: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 250 ICC (uA) 30.2.12 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-88. ATmega48PA: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-89. ATmega48PA: AREF External Reference Current vs. VCC 160 85 °C 25 °C -40 °C 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-90. ATmega48PA: Brownout Detector Current vs. VCC 40 ICC (uA) 32 85 °C 25 °C -40 °C 24 16 8 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-91. ATmega48PA: Programming Current vs. VCC 6 -40 °C 5 25 °C ICC (mA) 4 3 85 °C 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-92. ATmega48PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) ICC (mA) 0.14 0.12 5.5 V 0.1 5.0 V 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 0.02 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-93. ATmega48PA: Reset Supply Current vs. Frequency (1 - 20MHz) 2.5 5.5 V 2 5.0 V 4.5 V ICC (mA) 30.2.13 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-94. ATmega48PA: Minimum Reset Pulse width vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.1 ATmega88A Typical Characteristics Active Supply Current Figure 30-95. ATmega88A: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.3 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-96. ATmega88A: Active Supply Current vs. Frequency (1 - 20MHz) 12 5.5 V 10 5.0 V ICC (mA) 8 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-97. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.12 -40 °C 25 °C 85 °C ICC (mA) 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-98. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C 1 -40 °C ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-99. ATmega88A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C 5 -40 °C ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 30-100.ATmega88A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.15 5.5 V 0.12 ICC (mA) 5.0 V 0.09 4.5 V 4.0 V 0.06 3.3 V 2.7 V 0.03 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-101.ATmega88A: Idle Supply Current vs. Frequency (1-20MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 30.3.2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-102.ATmega88A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.04 85 °C ICC (mA) 0.03 25 °C -40 °C 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-103.ATmega88A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-104.ATmega88A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 1.2 85 °C 25 °C -40 °C ICC (mA) 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.3.3 ATmega88A: Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-5.
Power-down Supply Current Figure 30-105.ATmega88A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1.6 85 °C 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 25 °C 0.2 -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-106.ATmega88A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 85 °C -40 °C 25 °C 6 ICC (uA) 30.3.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.3.5 Power-save Supply Current Figure 30-107.ATmega88A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 3 2.5 85 °C ICC (uA) 2 -40 °C 1.5 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-108.ATmega88A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 0.12 ICC (mA) 30.3.6 4MHz_res 4MHz_xtal 0.1 0.08 2MHz_res 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.
Pin Pull-Up Figure 30-109.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 30-110.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 80 70 60 50 IOP (uA) 30.3.7 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 30-111.ATmega88A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 1 2 3 4 5 VOP (V) Figure 30-112.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-113.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-114.ATmega88A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) 120 100 IRESET (uA) 80 60 40 25 °C -40 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Driver Strength Figure 30-115.ATmega88A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-116.ATmega88A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) 30.3.8 -40 °C 0.3 0.2 0.
Figure 30-117.ATmega88A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-118.)ATmega88A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 4.
Pin Threshold and Hysteresis Figure 30-119.ATmega88A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 85 °C -40 °C 25 °C 3 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-120.ATmega88A: I/O Pin Input Threshold , Voltage vs. VCC (VIL, I/O Pin read as ‘0’ -40 °C 85 °C 25 °C 2.5 2 Threshold (V) 30.3.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-121.ATmega88A: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-122.ATmega88A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) -40 °C 1.5 25 °C 85 °C Threshold (V) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-123.ATmega88A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-124.ATmega88A: Reset Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 25 °C -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-125.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.83 Rising Vcc 1.82 Threshold (V) 1.81 1.8 1.79 Falling Vcc 1.78 1.77 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature (°C) Figure 30-126.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.3.10 2.7 Falling Vcc 2.68 2.66 2.
Figure 30-127.ATmega88A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.34 Rising Vcc 4.32 Threshold (V) 4.3 4.28 Falling Vcc 4.26 4.24 4.22 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-128.ATmega88A: Bandgap Voltage vs. VCC 1.103 Bandgap Voltage (V) 1.102 1.101 1.1 25 °C 1.099 1.098 -40 °C 85 °C 1.097 1.096 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-129.ATmega88A: Watchdog Oscillator Frequency vs. Temperature 114 113 112 FRC (kHz) 111 110 109 108 2.7 V 3.3 V 4.0 V 5.5 V 107 106 105 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-130.ATmega88A: Watchdog Oscillator Frequency vs. VCC 116 114 -40 °C 112 FRC (kHz) 30.3.11 25 °C 110 108 106 85 °C 104 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-131.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85 °C 8.2 FRC (MHz) 8.1 25 °C 8 7.9 -40 °C 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-132.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.0 V 8.2 FRC (MHz) 3.0 V 8.1 8 7.9 7.
Figure 30-133.ATmega88A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 14 85 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-134.ATmega88A: ADC Current vs. VCC (AREF = AVCC) -40 °C 25 °C 85 °C 300 250 200 ICC (uA) 30.3.12 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-135.ATmega88A: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-136.ATmega88A: AREF External Reference Current vs. VCC 85 °C 25 °C -40 °C 160 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-137.ATmega88A: Brownout Detector Current vs. VCC 50 ICC (uA) 40 30 85 °C 25 °C 20 -40 °C 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-138.ATmega88A: Programming Current vs. VCC 8 -40 °C 25 °C 7 6 85 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-139.ATmega88A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-140.ATmega88A: Reset Supply Current vs. Frequency (1 - 20MHz) 2 5.5 V 5.0 V 1.6 4.5 V ICC (mA) 30.3.13 1.2 4.0 V 0.8 3.3 V 0.4 2.7 V 1.
Figure 30-141.ATmega88A: Minimum Reset Pulse width vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.4.1 ATmega88PA Typical Characteristics Active Supply Current Figure 30-142.ATmega88PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.4 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-143.ATmega88PA: Active Supply Current vs. Frequency (1 - 20MHz) 12 5.5 V 10 5.0 V ICC (mA) 8 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-144.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.12 -40 °C 25 °C 85 °C ICC (mA) 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-145.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C 1 -40 °C ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-146.ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C 5 -40 °C ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 30-147.ATmega88PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.15 5.5 V 0.12 ICC (mA) 5.0 V 0.09 4.5 V 4.0 V 0.06 3.3 V 2.7 V 0.03 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-148.ATmega88PA: Idle Supply Current vs. Frequency (1 - 20MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 30.4.2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-149.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.04 85 °C ICC (mA) 0.03 25 °C -40 °C 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-150.ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-151.ATmega88PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 1.2 85 °C 25 °C -40 °C ICC (mA) 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.4.3 ATmega88PA: Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-7.
Power-down Supply Current Figure 30-152.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1.6 85 °C 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 25 °C 0.2 -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-153.ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 85 °C -40 °C 25 °C 6 ICC (uA) 30.4.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.4.5 Power-save Supply Current Figure 30-154.ATmega88PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal OscillatorWATCHDOG Running) TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 3 2.5 85 °C ICC (uA) 2 -40 °C 1.5 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-155.ATmega88PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 0.12 ICC (mA) 30.4.6 4MHz_res 4MHz_xtal 0.1 0.
Pin Pull-Up Figure 30-156.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 30-157.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 80 70 60 50 IOP (uA) 30.4.7 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 30-158.ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 1 2 3 4 5 VOP (V) Figure 30-159.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-160.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-161.ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) 120 100 IRESET (uA) 80 60 40 25 °C -40 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Driver Strength Figure 30-162.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-163.ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) 30.4.8 -40 °C 0.3 0.2 0.
Figure 30-164.ATmega88PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-165.ATmega88PA: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 4.
Pin Threshold and Hysteresis Figure 30-166.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 85 °C -40 °C 25 °C 3 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-167.ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) -40 °C 2.5 85 °C 25 °C 2 Threshold (V) 30.4.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-168.ATmega88PA: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-169.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) -40 °C 1.5 25 °C 85 °C Threshold (V) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-170.ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-171.ATmega88PA: Reset Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 25 °C -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-172.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.83 Rising Vcc 1.82 Threshold (V) 1.81 1.8 1.79 Falling Vcc 1.78 1.77 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-173.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.4.10 2.7 Falling Vcc 2.68 2.66 2.
Figure 30-174.ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.34 Rising Vcc 4.32 Threshold (V) 4.3 4.28 Falling Vcc 4.26 4.24 4.22 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-175.ATmega88PA: Bandgap Voltage vs. VCC 1.103 Bandgap Voltage (V) 1.102 1.101 1.1 25 °C 1.099 1.098 -40 °C 85 °C 1.097 1.096 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-176.ATmega88PA: Watchdog Oscillator Frequency vs. Temperature 114 113 112 FRC (kHz) 111 110 109 108 2.7 V 3.3 V 4.0 V 5.5 V 107 106 105 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-177.ATmega88PA: Watchdog Oscillator Frequency vs. VCC 116 114 -40 °C 112 FRC (kHz) 30.4.11 25 °C 110 108 106 85 °C 104 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-178.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85 °C 8.2 FRC (MHz) 8.1 25 °C 8 7.9 -40 °C 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-179.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.0 V 8.2 FRC (MHz) 3.0 V 8.1 8 7.9 7.
Figure 30-180.ATmega88PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 14 85 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-181.ATmega88PA: ADC Current vs. VCC (AREF = AVCC) -40 °C 25 °C 85 °C 300 250 200 ICC (uA) 30.4.12 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-182.ATmega88PA: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-183.ATmega88PA: AREF External Reference Current vs. VCC 85 °C 25 °C -40 °C 160 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-184.ATmega88PA: Brownout Detector Current vs. VCC 50 ICC (uA) 40 30 85 °C 25 °C 20 -40 °C 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-185.ATmega88PA: Programming Current vs. VCC 8 -40 °C 25 °C 7 6 85 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-186.ATmega88PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-187.ATmega88PA: Reset Supply Current vs. Frequency (1 - 20MHz) 2 5.5 V 5.0 V 1.6 4.5 V ICC (mA) 30.4.13 1.2 4.0 V 0.8 3.3 V 0.4 2.7 V 1.
Figure 30-188.ATmega88PA: Minimum Reset Pulse width vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.5.1 ATmega168A Typical Characteristics Active Supply Current Figure 30-189.ATmega168A: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.5 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-190.ATmega168A: Active Supply Current vs. Frequency (1-20MHz) 12 5.5 V 10 5.0 V ICC (mA) 8 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-191.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.15 -40 °C 85 °C 25 °C ICC (mA) 0.12 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-192.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-193.ATmega168A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 30-194.ATmega168A: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.15 5.5 V ICC (mA) 0.12 5.0 V 4.5 V 0.09 4.0 V 0.06 3.3 V 2.7 V 0.03 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-195.ATmega168A: Idle Supply Current vs. Frequency (1-20MHz) 3 5.5 V 2.5 5.0 V 2 ICC (mA) 30.5.2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-196.IATmega168A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.04 85 °C 0.035 0.03 25 °C -40 °C ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-197.ATmega168A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.3 85 °C 25 °C -40 °C 0.25 ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-198.ATmega168A: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 1.2 85 °C 25 °C -40 °C ICC (mA) 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.5.3 ATmega168A Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-9.
Power-down Supply Current Figure 30-199.ATmega168A: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1 85 °C ICC (uA) 0.8 0.6 0.4 0.2 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-200.ATmega168A: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 -40 °C 85 °C 25 °C 6 ICC (uA) 30.5.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.5.5 Power-save Supply Current Figure 30-201.ATmega168A: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2 ICC (uA) 1.5 -40 °C 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-202.ATmega168A: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 6MHz_xtal 6MHz_res 0.14 0.12 4MHz_res 4MHz_xtal 0.1 ICC(mA) 30.5.6 0.08 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.06 0.04 0.02 0 1.5 2 2.
Pin Pull-Up Figure 30-203.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 30-204.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 80 70 60 50 IOP (uA) 30.5.7 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 30-205.ATmega168A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 20 -40 °C 85 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 30-206.ATmega168A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-207.ATmega168A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-208.ATmega168A: Reset Pull-up Resistor Current vs.
Pin Driver Strength Figure 30-209.ATmega168A: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-210.ATmega168A: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C -40 °C 0.4 VOL (V) 30.5.8 0.3 0.2 0.
Figure 30-211.ATmega168A: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-212.ATmega168A: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 VOH (V) 4.8 4.6 -40 °C 25 °C 85 °C 4.4 4.
Pin Threshold and Hysteresis Figure 30-213.ATmega168A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-214.ATmega168A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 85 °C 25 °C -40 °C 2.5 2 Threshold (V) 30.5.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-215.ATmega168A: I/O Pin Input Hysteresis vs. VCC 85 °C 25 °C -40 °C 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-216.ATmega168A: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 85 °C -40 °C 25 °C 1.5 Threshold (V) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-217.ATmega168A: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-218.ATmega168A: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 0.1 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-219.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.86 1.84 Rising Vcc Threshold (V) 1.82 1.8 Falling Vcc 1.78 1.76 1.74 1.72 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-220.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.5.10 2.7 2.68 Falling Vcc 2.66 2.64 2.
Figure 30-221.ATmega168A: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.34 4.32 Rising Vcc Threshold (V) 4.3 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-222.ATmega168A: Bandgap Voltage vs. VCC 1.135 1.133 Bandgap Voltage (V) 1.131 1.129 85 °C 1.127 25 °C 1.125 1.123 1.121 1.119 -40 °C 1.117 1.115 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-223.ATmega168A: Watchdog Oscillator Frequency vs. Temperature 121 FRC (kHz) 119 117 115 2.7 V 113 3.3 V 5.5 V 111 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-224.ATmega168A: Watchdog Oscillator Frequency vs. VCC 122 120 -40 °C 118 FRC (kHz) 30.5.11 25 °C 116 114 112 85 °C 110 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-225.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8,4 85 °C 8.2 FRC (MHz) 25 °C 8 7.8 -40 °C 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-226.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 5.0 V 2.7 V 8.2 FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.
Figure 30-227.ATmega168A: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 16 85 °C 25 °C 14 -40 °C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-228.ATmega168A: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 ICC (uA) 30.5.12 250 200 150 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-229.ATmega168A: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 ICC (uA) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-230.ATmega168A: AREF External Reference Current vs. VCC 180 25 °C 160 85 °C -40 °C 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-231.ATmega168A: Brownout Detector Current vs. VCC 26 85 °C 24 25 °C ICC (uA) 22 -40 °C 20 18 16 14 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-232.ATmega168A: Programming Current vs. VCC ICC (mA) 10 8 -40 °C 25 °C 6 85 °C 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-233.ATmega168A: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-234.ATmega168A: Reset Supply Current vs. Frequency (1 - 20MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 30.5.13 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-235.ATmega168A: Minimum Reset Pulse width vs. VCC 1750 1500 Pulsewidth (ns) 1250 1000 750 500 85 °C 25 °C -40 °C 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.6.1 ATmega168PA Typical Characteristics Active Supply Current Figure 30-236.ATmega168PA: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 30.6 0.6 4.0 V 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-237.ATmega168PA: Active Supply Current vs. Frequency (1-20MHz) 12 5.5 V 10 5.0 V ICC (mA) 8 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-238.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.15 -40 °C 85 °C 25 °C ICC (mA) 0.12 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-239.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-240.ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 30-241.ATmega168PA: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.15 5.5 V ICC (mA) 0.12 5.0 V 4.5 V 0.09 4.0 V 0.06 3.3 V 2.7 V 0.03 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-242.ATmega168PA: Idle Supply Current vs. Frequency (1-20MHz) 3 5.5 V 2.5 5.0 V 2 ICC (mA) 30.6.2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-243.IATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.04 85 °C 0.035 0.03 25 °C -40 °C ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-244.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.3 85 °C 25 °C -40 °C 0.25 ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-245.ATmega168PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 1.2 85 °C 25 °C -40 °C ICC (mA) 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.6.3 ATmega168PA Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-11.
Power-down Supply Current Figure 30-246.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1 85 °C ICC (uA) 0.8 0.6 0.4 0.2 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-247.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 8 -40 °C 85 °C 25 °C 6 ICC (uA) 30.6.4 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.6.5 Power-save Supply Current Figure 30-248.ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2 ICC (uA) 1.5 -40 °C 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-249.ATmega168PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 6MHz_xtal 6MHz_res 0.14 0.12 4MHz_res 4MHz_xtal 0.1 ICC(mA) 30.6.6 0.08 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.06 0.04 0.02 0 1.5 2 2.
Pin Pull-Up Figure 30-250.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 30-251.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 80 70 60 50 IOP (uA) 30.6.7 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 30-252.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 20 -40 °C 85 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 30-253.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-254.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-255.ATmega168PA: Reset Pull-up Resistor Current vs.
Pin Driver Strength Figure 30-256.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 30-257.ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C -40 °C 0.4 VOL (V) 30.6.8 0.3 0.2 0.
Figure 30-258.ATmega168PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 30-259.ATmega168PA: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5 VOH (V) 4.8 4.6 -40 °C 25 °C 85 °C 4.4 4.
Pin Threshold and Hysteresis Figure 30-260.ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-261.ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 85 °C 25 °C -40 °C 2.5 2 Threshold (V) 30.6.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-262.ATmega168PA: I/O Pin Input Hysteresis vs. VCC 85 °C 25 °C -40 °C 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-263.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 85 °C -40 °C 25 °C 1.5 Threshold (V) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-264.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-265.ATmega168PA: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 85 °C 0.1 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-266.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.86 1.84 Rising Vcc Threshold (V) 1.82 1.8 Falling Vcc 1.78 1.76 1.74 1.72 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-267.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.76 Rising Vcc 2.74 2.72 Threshold (V) 30.6.10 2.7 2.68 Falling Vcc 2.66 2.64 2.
Figure 30-268.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.34 4.32 Rising Vcc Threshold (V) 4.3 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-269.ATmega168PA: Bandgap Voltage vs. VCC 1.135 1.133 Bandgap Voltage (V) 1.131 1.129 85 °C 1.127 25 °C 1.125 1.123 1.121 1.119 -40 °C 1.117 1.115 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-270.ATmega168PA: Watchdog Oscillator Frequency vs. Temperature 121 FRC (kHz) 119 117 115 2.7 V 113 3.3 V 5.5 V 111 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-271.ATmega168PA: Watchdog Oscillator Frequency vs. VCC 122 120 -40 °C 118 FRC (kHz) 30.6.11 25 °C 116 114 112 85 °C 110 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-272.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8,4 85 °C 8.2 FRC (MHz) 25 °C 8 7.8 -40 °C 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-273.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 5.0 V 2.7 V 8.2 FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.
Figure 30-274.ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 16 85 °C 25 °C 14 -40 °C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-275.ATmega168PA: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 ICC (uA) 30.6.12 250 200 150 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-276.ATmega168PA: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 85 °C 80 ICC (uA) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-277.ATmega168PA: AREF External Reference Current vs. VCC 180 25 °C 160 85 °C -40 °C 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-278.ATmega168PA: Brownout Detector Current vs. VCC 26 85 °C 24 25 °C ICC (uA) 22 -40 °C 20 18 16 14 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-279.ATmega168PA: Programming Current vs. VCC ICC (mA) 10 8 -40 °C 25 °C 6 85 °C 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-280.ATmega168PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-281.ATmega168PA: Reset Supply Current vs. Frequency (1 - 20MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 30.6.13 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
Figure 30-282.ATmega168PA: Minimum Reset Pulse width vs. VCC 1750 1500 Pulsewidth (ns) 1250 1000 750 500 85 °C 25 °C -40 °C 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.7.1 ATmega328 Typical Characteristics Active Supply Current Figure 30-283.ATmega328: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1.2 5.5 V 1 5.0 V 0.8 ICC (mA) 30.7 4.5 V 4.0 V 0.6 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-284.ATmega328: Active Supply Current vs. Frequency (1-20MHz) ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-285.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.16 85 °C 25 °C -40 °C ICC (mA) 0.12 0.08 0.04 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-286.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C 1.2 -40 °C ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-287.ATmega328: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 8 7 85 °C 6 25 °C -40 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 30-288.ATmega328: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.2 5.5 V 0.16 ICC (mA) 5.0 V 4.5 V 0.12 4.0 V 3.3 V 0.08 2.7 V 0.04 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-289.ATmega328: Idle Supply Current vs. Frequency (1-20MHz) 4 3.5 I CC (mA) 30.7.2 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-290.ATmega328: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.06 ICC (mA) 0.05 0.04 85 °C 0.03 25 °C -40 °C 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-291.ATmega328: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.4 85 °C 0.35 25 °C 0.3 -40 °C ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-292.ATmega328: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 2 85 °C 1.6 ICC (mA) 25 °C -40 °C 1.2 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.7.3 ATmega328 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
Table 30-14. ATmega328: Additional Current Consumption (percentage) in Active and Idle mode Additional Current consumption compared to Active with external clock (see Figure 30-330 on page 493 and Figure 30-331 on page 493) Additional Current consumption compared to Idle with external clock (see Figure 30-335 on page 495 and Figure 30-336 on page 496) PRUSART0 1.4% 7.8% PRTWI 3.0% 16.6% PRTIM2 3.3% 17.8% PRTIM1 2.7% 14.5% PRTIM0 0.9% 4.8% PRSPI 2.9% 15.7% PRADC 4.1% 22.
Figure 30-294.ATmega328: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 10 9 -40 °C 85 °C 25 °C 8 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 30-295.ATmega328: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2 1.8 1.6 25 °C 1.4 1.2 ICC (uA) 30.7.5 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.7.6 Standby Supply Current Figure 30-296.ATmega328: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.16 6MHz_res 6MHz_xtal 0.14 0.12 4MHz_res 4MHz_xtal ICC (mA) 0.1 0.08 2MHz_res 2MHz_xtal 0.06 1MHz_res 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-Up Figure 30-297.ATmega328: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 60 50 40 IOP (uA) 30.7.7 30 20 10 25 °C 0 85 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-298.ATmega328: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 90 80 70 IOP (uA) 60 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-299.ATmega328: I/O Pin Pull-up Resistor Current vs.
Figure 30-300.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 30 IRESET (uA) 25 20 15 10 25 °C 5 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET(V) Figure 30-301.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 70 60 IRESET (uA) 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.
Figure 30-302.ATmega328: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) 120 100 IRESET(uA) 80 60 40 25 °C 20 85 °C -40 °C 0 0 1 2 3 4 5 6 VRESET(V) Pin Driver Strength Figure 30-303.ATmega328: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C 0.6 V OL (V) 30.7.8 -40 °C 0.4 0.
Figure 30-304.ATmega328: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C V OL (V) 0.4 -40 °C 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 30-305.ATmega328: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 V OH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.
Figure 30-306.ATmega328: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 0 5 10 15 20 25 IOH (mA) Pin Threshold and Hysteresis Figure 30-307.ATmega328: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 4 3.5 -40 °C 25 °C 85 °C 3 Threshold (V) 30.7.9 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-308.ATmega328: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-309.ATmega328: I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.7 -40 °C 25 °C 85 °C 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-310.ATmega328: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 2.5 -40 °C 25 °C Threshold (V) 2 85 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-311.ATmega328: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C Threshold (V) 2 -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-312.ATmega328: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -40 °C 0.1 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Threshold Figure 30-313.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.85 1.83 1 Threshold (V) 30.7.10 1.81 0 1.79 1.77 1.
Figure 30-314.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.78 2.76 1 Threshold (V) 2.74 2.72 2.7 2.68 0 2.66 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-315.ATmega328: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.4 Threshold (V) 4.35 1 4.3 0 4.
Figure 30-316.ATmega328: Bandgap Voltage vs. VCC 1.138 Bandgap Voltage (V) 1.136 1.134 25 °C 1.132 1.13 1.128 85 °C -40 °C 1.126 1.124 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Internal Oscillator Speed Figure 30-317.ATmega328: Watchdog Oscillator Frequency vs. Temperature 119 118 117 116 F RC (kHz) 30.7.11 115 114 113 112 2.7 V 111 3.3 V 110 4.0 V 5.
Figure 30-318.ATmega328: Watchdog Oscillator Frequency vs. VCC 120 118 -40 °C F RC (kHz) 116 25 °C 114 112 110 85 °C 108 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-319.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8.4 85 °C 8.2 F RC (MHz) 25 °C 8 -40 °C 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-320.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.4 8.3 5.0 V 8.2 3.0 V F RC (MHz) 8.1 8 7.9 7.8 7.7 7.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 30-321.ATmega328: Calibrated 8MHz RC Oscillator Frequency vs.
Current Consumption of Peripheral Units Figure 30-322.ATmega328: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-323.ATmega328: Analog Comparator Current vs. VCC 120 100 -40 °C 25 °C 85 °C 80 ICC (uA) 30.7.12 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-324.ATmega328: AREF External Reference Current vs. VCC 180 85 °C 25 °C -40 °C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-325.ATmega328: Brownout Detector Current vs. VCC 30 85 °C 25 °C -40 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-326.ATmega328: Programming Current vs. VCC 10 9 25 °C 85 °C -40 °C 8 ICC (mA) 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 30-327.ATmega328: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.15 5.5 V 5.0 V 4.5 V 0.1 4.0 V ICC (mA) 30.7.13 3.3 V 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-328.ATmega328: Reset Supply Current vs. Frequency (1 - 20MHz) 3 5.5 V 2.5 5.0 V 4.5 V ICC (mA) 2 4.0 V 1.5 1 3.3 V 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-329.ATmega328: Minimum Reset Pulse width vs. VCC 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active Supply Current Figure 30-330.ATmega328P: Active Supply Current vs. Low Frequency (0.1-1.0MHz) 1.2 5.5 V 1 5.0 V 0.8 ICC (mA) 30.8.1 ATmega328P Typical Characteristics 4.5 V 4.0 V 0.6 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-331.ATmega328P: Active Supply Current vs. Frequency (1-20MHz) 14 ICC (mA) 30.8 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
Figure 30-332.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.16 85 °C 25 °C -40 °C ICC (mA) 0.12 0.08 0.04 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-333.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C 1.2 -40 °C ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-334.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 8 7 85 °C 6 25 °C -40 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 30-335.ATmega328P: Idle Supply Current vs. Low Frequency (0.1-1.0MHz) 0.2 5.5 V 0.16 5.0 V ICC (mA) 30.8.2 4.5 V 0.12 4.0 V 3.3 V 0.08 2.7 V 0.04 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-336.ATmega328P: Idle Supply Current vs. Frequency (1-20MHz) 4 I CC (mA) 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-337.ATmega328P: Idle Supply Current vs. VCC (Internal , RC Oscillator, 128kHz) 0.06 ICC (mA) 0.05 0.04 85 °C 0.03 25 °C -40 °C 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-338.ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.4 85 °C 0.35 25 °C 0.3 -40 °C ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-339.ATmega328P: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8MHz) 2 85 °C 1.6 ICC (mA) 25 °C -40 °C 1.2 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.8.3 ATmega328P Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for details. Table 30-15.
Power-down Supply Current Figure 30-340.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 1.2 85 °C 1 ICC (uA) 0.8 0.6 0.4 0.2 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-341.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 10 9 -40 °C 85 °C 25 °C 8 7 6 ICC (uA) 30.8.4 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.8.5 Power-save Supply Current Figure 30-342.ATmega328P: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2 1.8 1.6 25 °C 1.4 ICC (uA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 30-343.ATmega328P: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.16 6MHz_res 6MHz_xtal 0.14 0.12 4MHz_res 4MHz_xtal 0.1 ICC (mA) 30.8.6 0.08 2MHz_res 2MHz_xtal 0.06 1MHz_res 0.04 0.02 0 1.5 2 2.
Pin Pull-Up Figure 30-344.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) 60 50 IOP (uA) 40 30 20 10 25 °C 0 85 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 30-345.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) 90 80 70 60 IOP (uA) 30.8.7 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.
Figure 30-346.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 20 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 30-347.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) 40 35 30 IRESET (uA) 25 20 15 10 25 °C 5 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 30-348.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) 70 60 IRESET (uA) 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET(V) Figure 30-349.ATmega328P: Reset Pull-up Resistor Current vs.
Pin Driver Strength Figure 30-350.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V) 1 85 °C 0.8 25 °C V OL (V) 0.6 -40 °C 0.4 0.2 0 0 5 10 15 20 25 IOL (mA) Figure 30-351.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) 0.6 85 °C 0.5 25 °C 0.4 V OL (V) 30.8.8 -40 °C 0.3 0.2 0.
Figure 30-352.ATmega328P: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V) 3.5 3 V OH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 5 10 15 20 25 IOH (mA) Figure 30-353.ATmega328P: I/O Pin Output Voltage vs. Source Current (VCC = 5 V) 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
Pin Threshold and Hysteresis Figure 30-354.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) , 4 3.5 -40 °C 25 °C 85 °C Threshold (V) 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-355.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C -40 °C 2 Threshold (V) 30.8.9 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-356.ATmega328P: I/O Pin Input Hysteresis vs. VCC 0.7 -40 °C 25 °C 85 °C 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-357.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 2.5 -40 °C 25 °C Threshold (V) 2 85 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-358.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 85 °C 25 °C Threshold (V) 2 -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-359.ATmega328P: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -40 °C 0.1 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Threshold Figure 30-360.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V) 1.85 1.83 Threshold (V) 1 1.81 0 1.79 1.77 1.75 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-361.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.78 2.76 1 2.74 Threshold (V) 30.8.10 2.72 2.7 2.68 0 2.
Figure 30-362.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.4 Threshold (V) 4.35 1 4.3 0 4.25 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-363.ATmega328P: Bandgap Voltage vs. VCC 1.138 Bandgap Voltage (V) 1.136 1.134 25 °C 1.132 1.13 1.128 85 °C -40 °C 1.126 1.124 1.5 2 2.5 3 3.5 4 4.5 5 5.
Internal Oscillator Speed Figure 30-364.ATmega328P: Watchdog Oscillator Frequency vs. Temperature 119 118 117 F RC (kHz) 116 115 114 113 112 2.7 V 3.3 V 4.0 V 5.5 V 111 110 109 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 30-365.ATmega328P: Watchdog Oscillator Frequency vs. VCC 120 118 -40 °C 116 F RC (kHz) 30.8.11 25 °C 114 112 110 85 °C 108 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-366.ATmega328P: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.4 85 °C 8.2 F RC (MHz) 25 °C 8 -40 °C 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-367.ATmega328P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.4 8.3 5.0 V 8.2 3.0 V F RC (MHz) 8.1 8 7.9 7.8 7.7 7.
Figure 30-368.ATmega328P: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 16 14 85 °C 25 °C 12 -40 °C F RC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 30-369.ATmega328P: ADC Current vs. VCC (AREF = AVCC) 350 -40 °C 25 °C 85 °C 300 250 ICC (uA) 30.8.12 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-370.ATmega328P: Analog Comparator Current vs. VCC 120 100 -40 °C 25 °C 85 °C ICC (uA) 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-371.ATmega328P: AREF External Reference Current vs. VCC 180 85 °C 25 °C -40 °C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-372.ATmega328P: Brownout Detector Current vs. VCC 30 85 °C 25 °C -40 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-373.ATmega328P: Programming Current vs. VCC 10 9 25 °C 85 °C -40 °C 8 ICC (mA) 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 30-374.ATmega328P: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.15 5.5 V 5.0 V 4.5 V 0.1 ICC (mA) 4.0 V 3.3 V 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-375.ATmega328P: Reset Supply Current vs. Frequency (1 - 20MHz) 3 5.5 V 2.5 5.0 V 4.5 V 2 ICC (mA) 30.8.13 4.0 V 1.5 1 3.3 V 2.7 V 0.5 1.
Figure 30-376.ATmega328P: Minimum Reset Pulse width vs. VCC 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 237 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 235 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWS7 TWS6 TWS5 2-wire Serial Interface Data Register (0xB9) TWSR (0xB8) TWBR (0xB7) Reserved – (0xB6) ASSR – (0xB5) Reserved – 237 TWA3 TWA2 TWA1 TWA0 TWGCE 237 TWS4 TWS3 – TWPS1 TWPS0 236 2-wire Serial Interface Bit Rat
Address Name (0x79) ADCH Bit 7 Bit 6 Bit 5 ADC Data Register High byte Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x78) ADCL ADC Data Register Low byte (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) Reserved – – – – – – – – (0x72) Reserved – – – – – – – – (0x71) Reserved – – – – – – – – (0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 159 (0x
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33) Reserved – – – – – – – – 0x12 (0x32) Reserved – – – – – – – – 0x11 (0x31) Reserved – – – – – – – – 0x10 (0x30) Reserved – – – – – – – – 0x0F (0x2F) Reserved – – – – – – – – 0x0E (0x2E) Reserved – – – – – – – – 0x0D (0x2D) Reserved – – – – – – – – 0x0C
32.
Mnemonics Operands Description Operation Flags #Clocks BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR
Mnemonics WDR BREAK Note: Operands Description Watchdog Reset Break Operation (see specific descr. for WDR/timer) For On-chip Debug Only Flags #Clocks None None 1 N/A 1. These instructions are only available in ATmega168PA and ATmega328P.
33. Ordering Information 33.1 ATmega48A Speed (MHz) 20(3) Note: Power Supply (V) 1.8 - 5.5 Ordering Code(2) Package(1) ATmega48A-AU ATmega48A-AUR(5) ATmega48A-CCU ATmega48A-CCUR(5) ATmega48A-MMH(4) ATmega48A-MMHR(4)(5) ATmega48A-MU ATmega48A-MUR(5) ATmega48A-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Operational Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
33.2 ATmega48PA Speed (MHz)(3) 20 Note: Power Supply 1.8 - 5.
33.3 ATmega88A Speed (MHz) 20(3) Note: Power Supply (V) 1.8 - 5.5 Ordering Code(2) Package(1) ATmega88A-AU ATmega88A-AUR(5) ATmega88A-CCU ATmega88A-CCUR(5) ATmega88A-MMH(4) ATmega88A-MMHR(4)(5) ATmega88A-MU ATmega88A-MUR(5) ATmega88A-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Operational Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
33.4 ATmega88PA Speed (MHz)(3) 20 Note: Power Supply (V) 1.8 - 5.
33.5 ATmega168A Speed (MHz)(3) 20 Note: Power Supply (V) 1.8 - 5.5 Ordering Code(2) Package(1) ATmega168A-AU ATmega168A-AUR(5) ATmega168A-CCU ATmega168A-CCUR(5) ATmega168A-MMH(4) ATmega168A-MMHR(4)(5) ATmega168A-MU ATmega168A-MUR(5) ATmega168A-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Operational Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
33.6 ATmega168PA Speed (MHz)(3) 20 20 Note: Ordering Code(2) Package(1) 1.8 - 5.5 ATmega168PA-AU ATmega168PA-AUR(5) ATmega168PA-CCU ATmega168PA-CCUR(5) ATmega168PA-MMH(4) ATmega168PA-MMHR(4)(5) ATmega168PA-MU ATmega168PA-MUR(5) ATmega168PA-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 85C) 1.8 - 5.
33.7 ATmega328 Speed (MHz) 20(3) Note: Power Supply (V) 1.8 - 5.5 Ordering Code(2) Package(1) ATmega328-AU ATmega328-AUR(5) ATmega328-MMH(4) ATmega328-MMHR(4)(5) ATmega328-MU ATmega328-MUR(5) ATmega328-PU 32A 32A 28M1 28M1 32M1-A 32M1-A 28P3 Operational Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
33.8 ATmega328P Speed (MHz)(3) 20 Note: Power Supply (V) 1.8 - 5.5 Ordering Code(2) Package(1) ATmega328P-AU ATmega328P-AUR(5) ATmega328P-MMH(4) ATmega328P-MMHR(4)(5) ATmega328P-MU ATmega328P-MUR(5) ATmega328P-PU 32A 32A 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 85C) ATmega328P-AN ATmega328P-ANR(5) ATmega328P-MN ATmega328P-MNR(5) ATmega328P-PN 32A 32A 32M1-A 32M1-A 28P3 Industrial (-40C to 105C) Operational Range 1. This device can also be supplied in wafer form.
34. Packaging Information 34.1 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
34.2 32CC1 1 2 3 4 5 6 0.08 A B Pin#1 ID C D SIDE VIEW D E b1 F A1 E A A2 TOP VIEW E1 e 1 2 3 4 5 32-Øb 6 F D1 COMMON DIMENSIONS (Unit of Measure = mm) E D B A A1 BALL CORNER MIN NOM MAX A – – 0.60 A1 0.12 – – SYMBOL C e BOTTOM VIEW A2 0.25 b1 0.25 D 3.90 D1 Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel to the seating plane. Note2: Dimension “b1” is the solderable surface defined by the opening of the solder resist layer.
34.3 28M1 D C 1 2 Pin 1 ID 3 E SIDE VIEW A1 TOP VIEW A y D2 K 1 0.45 2 R 0.20 3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C L e 0.4 Ref (4x) Note: 0.20 REF D 3.95 4.00 4.05 D2 2.35 2.40 2.45 E 3.95 4.00 4.05 E2 2.35 2.40 2.45 e BOTTOM VIEW The terminal #1 ID is a Laser-marked Feature. NOTE 0.45 L 0.35 0.40 0.45 y 0.00 – 0.08 K 0.
34.4 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
34.5 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) NOM MAX – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 A eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN – SYMBOL E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
35. Errata 35.1 Errata ATmega48A The revision letter in this section refers to the revision of the ATmega48A device. 35.1.1 Rev. D • Analog MUX can be turned off when setting ACME bit • TWI Data setup time can be too short 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
35.3 Errata ATmega88A The revision letter in this section refers to the revision of the ATmega88A device. 35.3.1 Rev. F • Analog MUX can be turned off when setting ACME bit • TWI Data setup time can be too short 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
35.5 Errata ATmega168A The revision letter in this section refers to the revision of the ATmega168A device. 35.5.1 Rev. E • Analog MUX can be turned off when setting ACME bit • TWI Data setup time can be too short 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
35.7 Errata ATmega328 The revision letter in this section refers to the revision of the ATmega328 device. 35.7.1 Rev D • Analog MUX can be turned off when setting ACME bit • TWI Data setup time can be too short 1. Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
2. Unstable 32kHz Oscillator The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is inaccurate. Problem Fix/ Workaround None. 35.8 Errata ATmega328P The revision letter in this section refers to the revision of the ATmega328P device. 35.8.1 Rev D • Analog MUX can be turned off when setting ACME bit • TWI Data setup time can be too short 1.
35.8.4 Rev A • Unstable 32kHz Oscillator 1. Unstable 32kHz Oscillator The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is inaccurate. Problem Fix/ Workaround None.
36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev. 8271E – 07/2012 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 36.2 Rev. 8271D – 05/11 1. 2. 3. 4. 5. 6. 7. 8. 36.3 Updated Figure 1-1 on page 2. Overlined “RESET” in 28 MLF top view and in 32 MLF top view.
2. 3. 4. 36.4 Rev. 8271B – 04/10 1. 2. 3. 4. 5. 36.5 Updated the “SRAM Data Memory”, Figure 8-3 on page 18. Updated ”Ordering Information” on page 525 with CCU and CCUR code related to “32CC1” Package drawing. “32CC1” Package drawing added on ”Packaging Information” on page 533. Updated Table 9-8 with correct value for timer oscilliator at xtal2/tos2 Corrected use of SBIS instructions in assembly code examples. Corrected BOD and BODSE bits to R/W in Section 10.11.2 on page 44, Section 12.
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET] 8271E–AVR–07/2012 546
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pin Descriptions .........................................................................................................3 2 Overview ................................................................................................... 5 2.1Block Diagram ..............
9.7128kHz Internal Oscillator .......................................................................................33 9.8External Clock .........................................................................................................33 9.9Clock Output Buffer .................................................................................................34 9.10Timer/Counter Oscillator ........................................................................................34 9.
13.1Pin Change Interrupt Timing ..................................................................................71 13.2Register Description ..............................................................................................72 14 I/O-Ports .................................................................................................. 76 14.1Overview ................................................................................................................76 14.
18.1Features ..............................................................................................................142 18.2Overview ..............................................................................................................142 18.3Timer/Counter Clock Sources .............................................................................143 18.4Counter Unit ........................................................................................................143 18.
21.7AVR USART MSPIM vs. AVR SPI ......................................................................205 21.8Register Description ............................................................................................206 22 2-wire Serial Interface .......................................................................... 209 22.1Features ..............................................................................................................209 22.22-wire Serial Interface Bus Definition ........
26.2Addressing the Flash During Self-Programming .................................................262 26.3Register Description ............................................................................................267 27 Boot Loader Support – Read-While-Write Self-Programming ......... 269 27.1Features ..............................................................................................................269 27.2Overview ...........................................................................
30.4ATmega88PA Typical Characteristics .................................................................393 30.5ATmega168A Typical Characteristics .................................................................418 30.6ATmega168PA Typical Characteristics ...............................................................443 30.7ATmega328 Typical Characteristics ....................................................................468 30.8ATmega328P Typical Characteristics ........................................
36.4Rev. 8271B – 04/10 .............................................................................................545 36.5Rev. 8271A – 12/09 .............................................................................................545 Table of Contents .......................................................................................
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