User Manual

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is rec-
ommended that maximum frequency of an external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1
(1)
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1.
PSRSYNC
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Synchronization