User Manual

141
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
17.4 Register Description
17.4.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is writ-
ten to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted.
This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without
the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and
PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.
Bit 765432 1 0
0x23 (0x43) TSM
– – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value000000 0 0