User Manual

173
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
Figure 20-1. USART Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 2 and Table 14-9 on page 89 for USART0 pin placement.
20.3 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four
modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave
synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asyn-
chronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in
the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn
pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn
pin is only active when using synchronous mode.
PARITY
GENERATOR
UBRRn [H:L]
UDRn(Transmit)
UCSRnA UCSRnB UCSRnC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxDn
TxDn
PIN
CONTROL
UDRn (Receive)
PIN
CONTROL
XCKn
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver