User Manual

185
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
20.7.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will there-
fore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function
of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in
the buffer will be lost
20.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its con-
tents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error
condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to
flush the receive buffer.
Note: 1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
20.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchro-
nous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit,
thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on
the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
20.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 20-5 illustrates the sam-
pling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and
eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation
due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of
operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Assembly Code Example
(1)
USART_Flush:
in r16, UCSRnA
sbrs r16, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C Code Example
(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}