User Manual

19
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
8.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 8-4.
Figure 8-4. On-chip Data SRAM Access Cycles
8.4 EEPROM Data Memory
The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of
at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,
specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
”Memory Programming” on page 285 contains a detailed description on EEPROM Programming in SPI or Parallel
Programming mode.
8.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-2. A self-timing function, however, lets the user software
detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some pre-
cautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock fre-
quency used. See ”Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When
the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction