User Manual

196
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCS-
RnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn
pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn
Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the
TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Reg-
ister do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a
frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be
read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits.
Must be written before writing the low bits to UDRn.
20.11.4 UCSRnC – USART Control and Status Register n C
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 20-8.
Note: 1. See ”USART in SPI Mode” on page 199 for full description of the Master SPI Mode (MSPIM) operation
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 20-8. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)
(1)