User Manual
199
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
21. USART in SPI Mode
21.1 Features
• Full Duplex, Three-wire Synchronous Data Transfer
• Master Operation
• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
• LSB First or MSB First Data Transfer (Configurable Data Order)
• Queued Operation (Double Buffered)
• High Resolution Baud Rate Generator
• High Speed Operation (f
XCKmax
= f
CK
/2)
• Flexible Interrupt Generation
21.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master
SPI compliant mode of operation.
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master
control logic takes direct control over the USART resources. These resources include the transmitter and receiver
shift register and buffers, and the baud rate generator. The parity generator and checker, the data and clock recov-
ery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a
common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both
modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers
changes when using MSPIM.
21.3 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode
of operation only internal clock generation (i.e. master operation) is supported. The Data Direction Register for the
XCKn pin (DDR_XCKn) must therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly.
Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit
set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The
baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 21-1:
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
Table 21-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud
Rate
(1)
Equation for Calculating UBRRn
Value
Synchronous Master
mode
BAUD
f
OSC
2 UBRRn 1+
---------------------------------------=
UBRRn
f
OSC
2BAUD
-------------------- 1–=