User Manual

206
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
21.8 Register Description
The following section describes the registers used for SPI operation using the USART.
21.8.1 UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART
operation. See ”UDRn – USART I/O Data Register n” on page 194.
21.8.2 UCSRnA – USART MSPIM Control and Status Register n A
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
(i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and conse-
quently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new
data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically cleared when a transmit
complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate
a Transmit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is
empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see
description of the UDRIE bit). UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnA is written.
21.8.3 UCSRnB – USART MSPIM Control and Status Register n B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated
only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in
UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCS-
RnA is set.
Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn – – – – – UCSRnA
Read/Write R R/W R R R R R R
Initial Value 0 0 0 0 0 1 1 0
Bit 7 6543210
RXCIEn TXCIEn UDRIE RXENn TXENn – - - UCSRnB
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 1 1 0