User Manual

207
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA
is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port opera-
tion for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the receiver
in MSPI mode (i.e. setting RXENn=1 and TXENn=0) has no meaning since it is the transmitter that controls the
transfer clock and since only master mode is supported.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the
TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Reg-
ister do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnB is written.
21.8.4 UCSRnC – USART MSPIM Control and Status Register n C
• Bit 7:6 – UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 21-4. See ”UCSRnC – USART Control
and Status Register n C” on page 196 for full description of the normal USART operation. The MSPIM is enabled
when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write oper-
ation where the MSPIM is enabled.
• Bit 5:3 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnC is written.
• Bit 2 – UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is trans-
mitted first. Refer to the Frame Formats section page 4 for details.
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 – – – UDORDn UCPHAn UCPOLn UCSRnC
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 21-4. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 Reserved
1 1 Master SPI (MSPIM)