User Manual

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
• Bit 1 – UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn.
Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 – UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings
determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details.
21.8.5 USART MSPIM Baud Rate Registers – UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation.
See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 198.