User Manual

214
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
Figure 22-7. SCL Synchronization Between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read
from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master
can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing
Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA
line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several
masters are trying to address the same Slave, arbitration will continue into the data packet.
Figure 22-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
TA
low
TA
high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TB
low
TB
high
Masters Start
Counting Low Period
Masters Start
Counting High Period
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
START
Master A Loses
Arbitration, SDA
A
SDA