User Manual

233
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
in a multi master system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a
REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED
START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer.
Figure 22-19. Combining Several TWI Modes to Access a Serial EEPROM
22.8 Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more
of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be
allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situ-
ation is depicted below, where two masters are trying to transmit data to a Slave Receiver.
Figure 22-20. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave
nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will
occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another
Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait
until the bus is free and transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing
arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not
being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action.
This is summarized in Figure 22-21. Possible status values are given in circles.
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........
R1 R2
V
CC